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? 2011 microchip technology inc. ds22272b-page 1 mcp4706/4716/4726 features: ? output voltage resolutions: - 12-bit: mcp4726 - 10-bit: mcp4716 -8-bit: mcp4706 ? rail-to-rail output ? fast settling time of 6 s (typical) ? dac voltage reference options: -v dd -v ref pin ? output gain options: - unity (1x) - 2x, only when v ref pin is used as voltage source ? nonvolatile memory (eeprom): - auto recall of saved dac register setting - auto recall of saved device configuration (voltage reference, gain, power-down) ? power-down modes: - disconnects output buffer - selection of v out pull-down resistors (640 k ? , 125 k ? , or 1 k ? ) ? low-power consumption: - normal operation: 210 a typ. - power-down operation: 60 na typ. (pd1:pd0 = 11 ) ? single-supply operation: 2.7v to 5.5v ?i 2 c? interface: - eight available addresses - standard (100 kbps), fast (400 kbps), and high-speed (3.4 mbps) modes ? small 6-lead sot-23 and dfn (2x2) packages ? extended temperature range: -40c to +125c applications: ? set point or offset trimming ? sensor calibration ? low-power portable instrumentation ? pc peripherals ? data acquisition systems ? motor control package types description: the mcp4706/4716/4726 are single channel 8-bit, 10-bit, and 12-bit buffered voltage output digital-to- analog converters (dac) with nonvolatile memory and an i 2 c serial interface. this family will also be referred to as mcp47x6. the v ref pin or the device v dd can be selected as the dac?s reference voltage. when v dd is selected, v dd is connected internally to the dac reference circuit. when the v ref pin is used, the user can select the output buffer?s gain to 1 or 2. when the gain is 2, the v ref pin voltage should be limited to a maximum of v dd /2. the dac register value and configuration bits can be programmed to nonvolatile memory (eeprom). the nonvolatile memory holds the dac register and configuration bit values when the device is powered off. a device reset (such as a power-on reset) latches these stored values into the volatile memory. power-down modes enable system current reduction when the dac output voltage is not required. the v out pin can be configured to present a low, medium, or high resistance load. these devices have a two-wire i 2 c? compatible serial interface for standard (100 khz), fast (400 khz), or high-speed (3.4 mhz) mode. these devices are available in small 6-pin sot-23 and dfn 2x2 mm packages. 1 2 3 4 5 6 v out scl sda v ss sot-23-6 v dd mcp4706/16/26 2x2 dfn-6* scl sda v ss 1 2 3 6 5 4 v out ep 7 v dd * includes exposed t hermal pad (ep); see ta b l e 3 - 1 . v ref v ref 8-/10-/12-bit voltage output digital-to-analog converter with eeprom and i 2 c? interface
mcp4706/4716/4726 ds22272b-page 2 ? 2011 microchip technology inc. block diagram v dd v ss scl sda v out dac register eeprom pd1:pd0 op amp i 2 c? interface logic v rl 1k ? 125 k ? 640 k ? v dd buffer gain (1x or 2x) (g = 0 or 1 ) resistor ladder reference v ref1 :v ref0 selection control logic v ref v w pd1:pd0
? 2011 microchip technology inc. ds22272b-page 3 mcp4706/4716/4726 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss ................ -0.6v to +6.5v voltage on all pins with respect to v ss ................................................................................ -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd ) ....................................................................................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ....................................................................................20 ma maximum input current source/sunk by sda, scl pins ........................................................................................2 ma maximum output current sunk by sda output pin ......................................................................................25 ma maximum current out of v ss pin ...................................50 ma maximum current into v dd pin ......................................50 ma maximum current sourced by the v out pin ..................40 ma maximum current sunk by the v out pin........................40 ma maximum current sunk by the v ref pin .........................40 a package power dissipation (t a = +50c, t j = +150c) sot-23-6 .......................................................452 mw dfn-6 ..........................................................1098 mw storage temperature .....................................-65c to +150c ambient temperature with power applied ......................................................................-55c to +125c esd protection on all pins ???????????????????????????????????? ?? 6kv (hbm) ??????????????????????????????????????????????????????????????? ????????????????????? ?? 400v (mm) maximum junction temperature (t j ) ......................... +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this s pecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp4706/4716/4726 ds22272b-page 4 ? 2011 microchip technology inc. electrical characteristics electrical specifications: unless otherwise indicated, v dd = 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf, t a = -40c to +125c. typical values at +25c. parameters symbol min typical max units conditions power requirements input voltage v dd 2.7 ? 5.5 v input current i dd ? 210 400 a v ref1 :v ref0 = 00 , scl = sda = v ss , v out is unloaded, volatile dac register = 0 x 000 ? 210 400 a v ref1 :v ref0 = 11 , v ref = v dd , scl = sda = v ss , v out is unloaded, volatile dac register = 0 x 000 power-down current i ddp ? 0.09 2 a pd1:pd0 = 01 ( note 6 ), v out not connected power-on reset threshold v por ? 2.2 ? v ram retention voltage, (v ram ) < v por power-up ramp rate v ramp 1??v/s ( note 1 , note 4 ) note 1: this parameter is ensured by design and is not 100% tested. 2: this gain error does not include offset error. see section 2 for more details in plots. 3: within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 4: the power-up ramp rate affects on uploading the eeprom contents to the dac register. it measures the rise of v dd over time. 5: this parameter is ensured by characterization, and not 100% tested. 6: the pd1:pd0 = 10 , and ? 11 ? configurations should have the same current. 7: v dd = 5.5v.
? 2011 microchip technology inc. ds22272b-page 5 mcp4706/4716/4726 dc accuracy offset error v os 0.02 0.75 % of fsr code = 0x000h v ref1 :v ref0 = 00 , g = 0 offset error temperature coefficient v os /c ? 1 ? ppm/c -40c to +25c ? 2 ? ppm/c +25c to +85c zero-scale error e zs ? 0.13 2.0 lsb mcp4706, code = 0x00h ? 0.52 7.7 lsb mcp4716, code = 0x000h ? 2.05 30.8 lsb mcp4726, code = 0x000h full-scale error e fs ? 0.3 5.2 lsb mcp4706, code = 0xffh ? 1.1 20.5 lsb mcp4716, code = 0x3ffh ? 4.1 82.0 lsb mcp4726, code = 0xfffh gain error ( note 2 ) g e -2 -0.10 2 % of fsr mcp4706, code = 0xffh v ref1 :v ref0 = 00 , g = 0 -2 -0.10 2 % of fsr mcp4716, code = 0x3ffh v ref1 :v ref0 = 00 , g = 0 -2 -0.10 2 % of fsr mcp4726, code = 0xfffh v ref1 :v ref0 = 00 , g = 0 gain error drift ? g/c ? -3 ? ppm/c resolution n 8 bits mcp4706 10 bits mcp4716 12 bits mcp4726 inl error ( note 7 ) inl -0.907 0.125 +0.907 lsb mcp4706 (codes: 6 to 250) -3.625 0.5 +3.625 lsb mcp4716 (codes: 25 to 1000) -14.5 2 +14.5 lsb mcp4726 (codes: 100 to 4000) dnl error ( note 7 ) dnl -0.05 0.0125 +0.05 lsb mcp4706 (codes: 6 to 250) -0.188 0.05 +0.188 lsb mcp4716 (codes: 25 to 1000) -0.75 0.2 +0.75 lsb mcp4726 (codes: 100 to 4000) electrical characteristics (continued) electrical specifications: unless otherwise indicated, v dd = 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf, t a = -40c to +125c. typical values at +25c. parameters symbol min typical max units conditions note 1: this parameter is ensured by design and is not 100% tested. 2: this gain error does not include offset error. see section 2 for more details in plots. 3: within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 4: the power-up ramp rate affects on uploading the eeprom contents to the dac register. it measures the rise of v dd over time. 5: this parameter is ensured by characterization, and not 100% tested. 6: the pd1:pd0 = 10 , and ? 11 ? configurations should have the same current. 7: v dd = 5.5v.
mcp4706/4716/4726 ds22272b-page 6 ? 2011 microchip technology inc. output amplifier minimum output voltage v out(min) ? 0.01 ? v output amplifier?s minimum drive maximum output voltage v out(max) ?v dd ? 0.04 ? v output amplifier?s maximum drive phase margin pm ? 66 ? degree () c l = 400 pf, r l = ? slew rate sr ? 0.55 ? v/s short circuit current i sc 71524ma settling time t settling ?6?s note 3 power-down output disable time delay t pdd ? 1 ? s pd1:pd0 = 00 -> 11 , ? 10 ?, or ? 01 ? started from falling edge scl at end of ack bit. v out = v out - 10 mv. v out not connected. power-down output enable time delay t pde ? 10.5 ? s pd1:pd0 = 11 , ? 10 ?, or ? 01 ? -> ? 00 ? started from falling edge scl at end of ack bit. volatile dac register = ffh, v out =10mv. v out not connected. external reference (v ref ) ( note 1 ) input range v ref 0.04 ? v dd - 0.04 v buffered mode 0?v dd v unbuffered mode input impedance r vref ? 210 ? k ? unbuffered mode input capacitance c_ ref ? 29 ? pf unbuffered mode -3 db bandwidth ? 86.5 ? khz v ref = 2.048v 0.1v, v ref1 :v ref0 = 10 , g = 0 ?67.7? khzv ref = 2.048v 0.1v, v ref1 :v ref0 = 10 , g = 1 total harmonic distortion thd ? -73 ? db v ref = 2.048v 0.1v, v ref1 :v ref0 = 10 , g = 0 , frequency = 1 khz dynamic performance ( note 1 ) major code transition glitch ? 45 ? nv-s 1 lsb change around major carry (800h to 7ffh) digital feedthrough ? <10 ? nv-s electrical characteristics (continued) electrical specifications: unless otherwise indicated, v dd = 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf, t a = -40c to +125c. typical values at +25c. parameters symbol min typical max units conditions note 1: this parameter is ensured by design and is not 100% tested. 2: this gain error does not include offset error. see section 2 for more details in plots. 3: within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 4: the power-up ramp rate affects on uploading the eeprom contents to the dac register. it measures the rise of v dd over time. 5: this parameter is ensured by characterization, and not 100% tested. 6: the pd1:pd0 = 10 , and ? 11 ? configurations should have the same current. 7: v dd = 5.5v.
? 2011 microchip technology inc. ds22272b-page 7 mcp4706/4716/4726 digital interface output low voltage v ol ??0.4 v i ol = 3 ma input high voltage (sda and scl pins) v ih 0.7v dd ?? v input low voltage (sda and scl pins) v il ? ?0.3v dd v input leakage i li ? ? 1 a scl = sda = v ss or scl = sda = v dd pin capacitance c pin ?? 3 pf ( note 5 ) eeprom eeprom write time t write ?2550 ms data retention ? 200 ? years at +25c, ( note 1 ) endurance 1 ? ? million cycles at +25c, ( note 1 ) electrical characteristics (continued) electrical specifications: unless otherwise indicated, v dd = 2.7v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf, t a = -40c to +125c. typical values at +25c. parameters symbol min typical max units conditions note 1: this parameter is ensured by design and is not 100% tested. 2: this gain error does not include offset error. see section 2 for more details in plots. 3: within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 4: the power-up ramp rate affects on uploading the eeprom contents to the dac register. it measures the rise of v dd over time. 5: this parameter is ensured by characterization, and not 100% tested. 6: the pd1:pd0 = 10 , and ? 11 ? configurations should have the same current. 7: v dd = 5.5v.
mcp4706/4716/4726 ds22272b-page 8 ? 2011 microchip technology inc. 1.1 i 2 c mode timing waveforms and requirements figure 1-1: power-on and brown-out reset waveforms. figure 1-2: i 2 c power-down command timing. table 1-1: reset timing timing characteristics standard operating conditions (unless otherwise specified) operating temperature -40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions power-up reset delay t pord ? 60 ? s monitor ack bit response to ensure device responds to command. brown-out reset delay t bord ?1?sv dd transitions from v dd(min) ? > v por v out driven to v out disabled power-down disable time delay t pdd ?2.5? sv dd = 5v pd1:pd0 ? 00 (from ? 01 ?, ? 10 ?, or ? 11 ?), from falling edge scl at end of ack bit. ?5?sv dd = 3v pd1:pd0 ? 00 (from ? 01 ?, ? 10 ?, or ? 11 ?), from falling edge scl at end of ack bit. power-down enable time delay t pde ? 10.5 ? s pd1:pd0 ? 01 , ? 10 ?, or ? 11 ? (from ? 00 ?), from falling edge scl at end of ack bit. v dd sda t pord t bord v out scl v ih v ih v por (v bor ) v out pulled down by internal 500 k ? (typical) resistor i 2 c? interface is operational sda scl ack stop start ack v out t pde t pdd
? 2011 microchip technology inc. ds22272b-page 9 mcp4706/4716/4726 figure 1-3: i 2 c bus start/stop bits timing waveforms. table 1-2: i 2 c bus start/stop bits requirements i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in electrical characteristics param. no. symbol characteristic min max units conditions f scl scl pin frequency standard mode 0 100 khz c b = 400 pf, 2.7v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v high-speed 1.7 0 1.7 mhz c b = 400 pf, 4.5v - 5.5v high-speed 3.4 0 3.4 mhz c b = 100 pf, 4.5v - 5.5v d102 c b bus capacitive loading 100 khz mode ? 400 pf 400 khz mode ? 400 pf 1.7 mhz mode ? 400 pf 3.4 mhz mode ? 100 pf 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 92 t su : sto stop condition 100 khz mode 4000 ? ns setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 94 t hvcsu hvc to scl setup time 25 ? us high voltage commands 95 t hvchd scl to hvc hold time 25 ? us high voltage commands 91 93 scl sda start condition stop condition 90 92 v ih 111 v il
mcp4706/4716/4726 ds22272b-page 10 ? 2011 microchip technology inc. figure 1-4: i 2 c bus data timing. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out table 1-3: i 2 c bus data requirements (slave mode) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in electrical characteristics param. no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ? ns 2.7v-5.5v 400 khz mode 600 ? ns 2.7v-5.5v 1.7 mhz mode 120 ns 4.5v-5.5v 3.4 mhz mode 60 ? ns 4.5v-5.5v 101 t low clock low time 100 khz mode 4700 ? ns 2.7v-5.5v 400 khz mode 1300 ? ns 2.7v-5.5v 1.7 mhz mode 320 ns 4.5v-5.5v 3.4 mhz mode 160 ? ns 4.5v-5.5v note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 3: the mcp47x6 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use c b in pf for the calculations. 5: not tested. this parameter ensured by characterization. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. if this parameter is too short, it can create an unintentional start or stop condition to other devices on the i 2 c bus line. if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. data input: this parameter must be longer than t sp . data output: this parameter is characterized, and tested indirectly by testing t aa parameter. 7: ensured by the t aa 3.4 mhz specification test. 8: the specification is not part of the i 2 c specification. t aa = t hd:dat + t fsda (or t rsda ).
? 2011 microchip technology inc. ds22272b-page 11 mcp4706/4716/4726 102a (5) t rscl scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 1.7 mhz mode 20 160 ns after a repeated start condition or an acknowledge bit 3.4 mhz mode 10 40 ns 3.4 mhz mode 10 80 ns after a repeated start condition or an acknowledge bit 102b (5) t rsda sda rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 103a (5) t fscl scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 3.4 mhz mode 10 40 ns 103b (5) t fsda sda fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb (4) 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns table 1-3: i 2 c bus data requirements (slave mode) (continued) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in electrical characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 3: the mcp47x6 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use c b in pf for the calculations. 5: not tested. this parameter ensured by characterization. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. if this parameter is too short, it can create an unintentional start or stop condition to other devices on the i 2 c bus line. if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. data input: this parameter must be longer than t sp . data output: this parameter is characterized, and tested indirectly by testing t aa parameter. 7: ensured by the t aa 3.4 mhz specification test. 8: the specification is not part of the i 2 c specification. t aa = t hd:dat + t fsda (or t rsda ).
mcp4706/4716/4726 ds22272b-page 12 ? 2011 microchip technology inc. 106 t hd:dat data input hold time 100 khz mode 0 ? ns 2.7v-5.5v, note 6 400 khz mode 0 ? ns 2.7v-5.5v, note 6 1.7 mhz mode 0 ? ns 4.5v-5.5v, note 6 3.4 mhz mode 0 ? ns 4.5v-5.5v, note 6 107 t su:dat data input setup time 100 khz mode 250 ? ns note 2 400 khz mode 100 ? ns 1.7 mhz mode 10 ? ns 3.4 mhz mode 10 ? ns 109 t aa output valid from clock 100 khz mode ? 3750 ns note 1 , note 8 400 khz mode ? 1200 ns 1.7 mhz mode ? 150 ns cb = 100 pf, note 1 , note 7 , note 8 ? 310 ns cb = 400 pf, note 1 , note 5 , note 8 3.4 mhz mode ? 150 ns cb = 100 pf, note 1 , note 8 110 t buf bus free time 100 khz mode 4700 ? ns time the bus must be free before a new transmission can start 400 khz mode 1300 ? ns 1.7 mhz mode n/a ? ns 3.4 mhz mode n/a ? ns table 1-3: i 2 c bus data requirements (slave mode) (continued) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in electrical characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 3: the mcp47x6 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use c b in pf for the calculations. 5: not tested. this parameter ensured by characterization. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. if this parameter is too short, it can create an unintentional start or stop condition to other devices on the i 2 c bus line. if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. data input: this parameter must be longer than t sp . data output: this parameter is characterized, and tested indirectly by testing t aa parameter. 7: ensured by the t aa 3.4 mhz specification test. 8: the specification is not part of the i 2 c specification. t aa = t hd:dat + t fsda (or t rsda ).
? 2011 microchip technology inc. ds22272b-page 13 mcp4706/4716/4726 111 t sp input filter spike suppression (sda and scl) 100 khz mode ? 50 ns nxp spec states n/a 400 khz mode ? 50 ns 1.7 mhz mode ? 10 ns spike suppression 3.4 mhz mode ? 10 ns spike suppression ? ? ? ns standard mode, (not applicable) 50 (typ) ? ? ns fast mode 10 (typ) ? ? ns high-speed mode 1.7 10 (typ) ? ? ns high-speed mode 3.4 table 1-3: i 2 c bus data requirements (slave mode) (continued) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in electrical characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 3: the mcp47x6 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: use c b in pf for the calculations. 5: not tested. this parameter ensured by characterization. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. if this parameter is too short, it can create an unintentional start or stop condition to other devices on the i 2 c bus line. if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. data input: this parameter must be longer than t sp . data output: this parameter is characterized, and tested indirectly by testing t aa parameter. 7: ensured by the t aa 3.4 mhz specification test. 8: the specification is not part of the i 2 c specification. t aa = t hd:dat + t fsda (or t rsda ).
mcp4706/4716/4726 ds22272b-page 14 ? 2011 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters symbol min typical max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 6l-sot-23 ? ja ?190?c/w thermal resistance, 6l-dfn (2 x 2) ? ja ?91?c/w note 1: the mcp47x6 devices operate over this extended temperature range, but with reduced performance. operation in this range must not cause t j to exceed the maximum junction temperature of +150c.
? 2011 microchip technology inc. ds22272b-page 15 mcp4706/4716/4726 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-1: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-2: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-3: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-4: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 00 . figure 2-5: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 00 . figure 2-6: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 00 . note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb) -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb)
mcp4706/4716/4726 ds22272b-page 16 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-7: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-8: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-9: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 00 . figure 2-10: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 00 . figure 2-11: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 00 . figure 2-12: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 00 . -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb)
? 2011 microchip technology inc. ds22272b-page 17 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-13: zero-scale error (zse) vs. v dd and temperature ( mcp4726 ). v ref1 :v ref0 = 00 . figure 2-14: zero-scale error (zse) vs. v dd and temperature ( mcp4716 ). v ref1 :v ref0 = 00 . figure 2-15: zero-scale error (zse) vs. v dd and temperature ( mcp4706 ). v ref1 :v ref0 = 00 . figure 2-16: full-scale error (fse) vs. v dd and temperature ( mcp4726 ). v ref1 :v ref0 = 00 . figure 2-17: full-scale error (fse) vs. v dd and temperature ( mcp4716 ). v ref1 :v ref0 = 00 . figure 2-18: full-scale error (fse) vs. v dd and temperature ( mcp4706 ). v ref1 :v ref0 = 00 . 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.0 0.1 0.2 0.3 0.4 0.5 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.00 0.05 0.10 0.15 0.20 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -18.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -2.0 -1.5 -1.0 -0.5 0.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb)
mcp4706/4716/4726 ds22272b-page 18 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-19: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-20: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-21: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-22: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-23: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-24: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb) -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb)
? 2011 microchip technology inc. ds22272b-page 19 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-25: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-26: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-27: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-28: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-29: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-30: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb)
mcp4706/4716/4726 ds22272b-page 20 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-31: zero-scale error (zse) vs. temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-32: zero-scale error (zse) vs. temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-33: zero-scale error (zse) vs. temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-34: full-scale error (fse) vs. temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-35: full-scale error (fse) vs. temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-36: full-scale error (fse) vs. temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.0 0.1 0.2 0.3 0.4 0.5 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.00 0.05 0.10 0.15 0.20 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -18.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -2.0 -1.5 -1.0 -0.5 0.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb)
? 2011 microchip technology inc. ds22272b-page 21 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-37: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-38: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-39: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-40: inl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-41: inl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-42: inl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb) -12 -8 -4 0 4 8 12 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code inl error (lsb)
mcp4706/4716/4726 ds22272b-page 22 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-43: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-44: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-45: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-46: dnl vs. code (code = 100 to 4000) and temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-47: dnl vs. code (code = 25 to 1000) and temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-48: dnl vs. code (code = 6 to 250) and temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 1024 2048 3072 4096 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 -40c +25c +85c +125c volatile dac register code dnl error (lsb) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0 32 64 96 128 160 192 224 256 -40c +25c +85c +125c volatile dac register code dnl error (lsb)
? 2011 microchip technology inc. ds22272b-page 23 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-49: zero-scale error (zse) vs. temperature ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-50: zero-scale error (zse) vs. temperature ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-51: zero-scale error (zse) vs. temperature ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-52: full-scale error (fse) vs. temperature ( mcp4726 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-53: full-scale error (fse) vs. temperature ( mcp4716 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-54: full-scale error (fse) vs. temperature ( mcp4706 ). v dd = 2.7v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.0 0.1 0.2 0.3 0.4 0.5 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) 0.00 0.05 0.10 0.15 0.20 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) zero scale error (lsb) -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -18.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb) -2.0 -1.5 -1.0 -0.5 0.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) full scale error (lsb)
mcp4706/4716/4726 ds22272b-page 24 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-55: inl vs. code (code = 100 to 4000) and v dd (2.7v, 5v, 5.5v) ( mcp4726 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-56: inl vs. code (code = 25 to 1000) and v dd (2.7v, 5v, 5.5v) ( mcp4716 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-57: inl vs. code (code = 6 to 250) and v dd (2.7v, 5v, 5.5v) ( mcp4706 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-58: dnl vs. code (code = 100 to 4000) and v dd (2.7v, 5v, 5.5v) ( mcp4726 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-59: dnl vs. code (code = 25 to 1000) and v dd (2.7v, 5v, 5.5v) ( mcp4716 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-60: dnl vs. code (code = 6 to 250) and v dd (2.7v, 5v, 5.5v) ( mcp4706 ). v ref1 :v ref0 = 10 , g = 1 , v ref = v dd /2, temp = +25c. -8 -4 0 4 8 12 16 0 1024 2048 3072 4096 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 1024 2048 3072 4096 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 128 256 384 512 640 768 896 1024 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb) -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 32 64 96 128 160 192 224 256 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb)
? 2011 microchip technology inc. ds22272b-page 25 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-61: inl vs. code (code = 100 to 4000) and v dd (2.7v, 5v, 5.5v) ( mcp4726 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-62: inl vs. code (code = 25 to 1000) and v dd (2.7v, 5v, 5.5v) ( mcp4716 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-63: inl vs. code (code = 6 to 250) and v dd (2.7v, 5v, 5.5v) ( mcp4706 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-64: dnl vs. code (code = 100 to 4000) and v dd (2.7v, 5v, 5.5v) ( mcp4726 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-65: dnl vs. code (code = 25 to 1000) and v dd (2.7v, 5v, 5.5v) ( mcp4716 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. figure 2-66: dnl vs. code (code = 6 to 250) and v dd (2.7v, 5v, 5.5v) ( mcp4706 ). v ref1 :v ref0 = 11 , g = 1 , v ref = v dd /2, temp = +25c. -8 -4 0 4 8 12 16 0 1024 2048 3072 4096 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 2.7v 5.0v 5.5v volatile dac register code inl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 1024 2048 3072 4096 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 128 256 384 512 640 768 896 1024 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb) -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 32 64 96 128 160 192 224 256 2.7v 5.0v 5.5v volatile dac register code dnl error (lsb)
mcp4706/4716/4726 ds22272b-page 26 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-67: inl vs. code (code = 100 to 4000) and v ref ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-68: inl vs. code (code = 25 to 1000) and v ref ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-69: inl vs. code (code = 6 to 250) and v ref ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-70: dnl vs. code (code = 100 to 4000) and v ref ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-71: dnl vs. code (code = 25 to 1000) and v ref ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-72: dnl vs. code (code = 6 to 250) and v ref ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. -8 -4 0 4 8 12 16 0 1024 2048 3072 4096 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -2 -1 0 1 2 3 4 0 128 256 384 512 640 768 896 1024 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 1024 2048 3072 4096 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1024 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb)
? 2011 microchip technology inc. ds22272b-page 27 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-73: inl vs. code (code = 100 to 4000) and v ref ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-74: inl vs. code (code = 25 to 1000) and v ref ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-75: inl vs. code (code = 6 to 250) and v ref ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-76: dnl vs. code (code = 100 to 4000) and v ref ( mcp4726 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-77: dnl vs. code (code = 25 to 1000) and v ref ( mcp4716 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. figure 2-78: dnl vs. code (code = 6 to 250) and v ref ( mcp4706 ). v dd = 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = 1v, 2v, 3v, 4v, and 5v, temp = +25c. -8 -4 0 4 8 12 16 0 1024 2048 3072 4096 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -2 -1 0 1 2 3 4 0 128 256 384 512 640 768 896 1024 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 32 64 96 128 160 192 224 256 1v 2v 3v 4v 5v volatile dac register code inl error (lsb) -1.0 -0.5 0.0 0.5 1.0 0 1024 2048 3072 4096 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1024 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 1v 2v 3v 4v 5v volatile dac register code dnl error (lsb)
mcp4706/4716/4726 ds22272b-page 28 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-79: output error vs. temperature ( mcp4726 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 00 , code = 4000. figure 2-80: output error vs. temperature ( mcp4716 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 00 , code = 1000. figure 2-81: output error vs. temperature ( mcp4706 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 00 , code = 250. figure 2-82: output error vs. temperature ( mcp4726 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd , code = 4000. figure 2-83: output error vs. temperature ( mcp4716 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd , code = 1000. figure 2-84: output error vs. temperature ( mcp4706 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd , code = 250. -36.0 -34.0 -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -36.0 -34.0 -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb)
? 2011 microchip technology inc. ds22272b-page 29 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-85: output error vs. temperature ( mcp4726 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd , code = 4000. figure 2-86: output error vs. temperature ( mcp4716 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd , code = 1000. figure 2-87: output error vs. temperature ( mcp4706 ). v dd = 2.7v and 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd , code = 250. -36.0 -34.0 -32.0 -30.0 -28.0 -26.0 -24.0 -22.0 -20.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -8.0 -7.0 -6.0 -5.0 -4.0 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb) -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) output error (lsb)
mcp4706/4716/4726 ds22272b-page 30 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-88: i dd vs. temperature. v dd = 2.7v and 5v, v ref1 :v ref0 = 00 . figure 2-89: i dd vs. temperature. v dd = 2.7v and 5v, v ref1 :v ref0 = 10 , g = 0 , v ref = v dd . figure 2-90: i dd vs. temperature. v dd = 2.7v and 5v, v ref1 :v ref0 = 11 , g = 0 , v ref = v dd . figure 2-91: power-down current vs. temperature. v dd = 2.7v, 3.3v, 4.5v, 5.0v and 5.5v, pd1:pd0 = 11 . 100 125 150 175 200 225 250 -40 -20 0 20 40 60 80 100 120 2.7v 3.3v 4.5v 5.0v 5.5v temperature (c) i dd (ua) 100 125 150 175 200 225 250 -40 -20 0 20 40 60 80 100 120 2.7v 3.3v 4.5v 5.0v 5.5v temperature (c) i dd (ua) 100 125 150 175 200 225 250 -40 -20 0 20 40 60 80 100 120 2.7v 3.3v 4.5v 5.0v 5.5v temperature (c) i dd (ua) 0 100 200 300 400 500 -40 -20 0 20 40 60 80 100 120 2.7v 3.3v 4.5v 5.0v 5.5v temperature (c) i powerdown (na)
? 2011 microchip technology inc. ds22272b-page 31 mcp4706/4716/4726 note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v rl = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-92: v ih threshold of sda/scl inputs vs. temperature and v dd . figure 2-93: v il threshold of sda/scl inputs vs. temperature and v dd . figure 2-94: v out vs. resistive load. v dd = 5.0v. figure 2-95: v out vs. source/sink current. v dd = 5.0v. 50 55 60 65 70 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) v ih (% v dd ) 30 35 40 45 50 -40 -20 0 20 40 60 80 100 120 2.7v 5.0v 5.5v temperature (c) v il (% v dd ) 0 1 2 3 4 5 6 0 1000 2000 3000 4000 5000 load resistance (r l ) ( ) v out (v) code = fffh 0 1 2 3 4 5 6 03691215 i source/sink (ma) v out (v) code = fffh code = 000h
mcp4706/4716/4726 ds22272b-page 32 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v, v ref = internal, gain = x1, r l = 5 k ? , c l = 100 pf. figure 2-96: full-scale settling time (000h to fffh) ( mcp4726 ). figure 2-97: full-scale settling time (fffh to 000h) ( mcp4726 ). figure 2-98: half-scale settling time (400h to c00h) ( mcp4726 ). figure 2-99: half-scale settling time (c00h to 400h) ( mcp4726 ). figure 2-100: exiting power-down mode (mcp4726, volatile dac register = fffh).
? 2011 microchip technology inc. ds22272b-page 33 mcp4706/4716/4726 3.0 pin descriptions an overview of the pin functions are described in section 3.1 through section 3.7 . the descriptions of the pins are listed in ta b l e 3 - 1 . table 3-1: mcp47x6 pinout description pin standard function sot-23 dfn symbol i/o buffer type 6l 6l 16 v out a analog buffered analog voltage output pin 25v ss ? p ground reference pin for all circuitries on the device 34v dd ? p supply voltage pin 4 3 sda i/o st i 2 c? serial data pin 52 scl ist i 2 c serial clock pin 61v ref a analog voltage reference input pin ? 7 ep ? ? exposed pad note 1 legend: a = analog pins i = digital input (high z) o = digital output i/o = input / output p = power note 1: the dfn package has a contact on the bottom of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device?s v ss pin.
mcp4706/4716/4726 ds22272b-page 34 ? 2011 microchip technology inc. 3.1 analog output voltage pin (v out ) v out is the dac analog output pin. the dac output has an output amplifier. v out can swing from approximately 0v to approximately v dd . the full-scale range of the dac output is from v ss to g * v rl , where g is the gain selection option (1x or 2x). in normal mode, the dc impedance of the output pin is about 1 ? . in power-down mode, the output pin is internally connected to a known pull-down resistor of 1k ? , 125 k ? , or 640 k ? . the power-pown selection bits settings are shown tab l e 4 - 2 . 3.2 positive power supply input (v dd ) v dd is the positive supply voltage input pin. the input supply voltage is relative to v ss . the power supply at the v dd pin should be as clean as possible for a good dac performance. it is recommended to use an appropriate bypass capacitor of about 0.1 f (ceramic) to ground. an additional 10 f capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise present in application boards. 3.3 ground (v ss ) the v ss pin is the device ground reference. the user must connect the v ss pin to a ground plane through a low-impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.4 serial data pin (sda) sda is the serial data pin of the i 2 c interface. the sda pin is used to write or read the dac registers and con- figuration bits. the sda pin is an open-drain n-channel driver. therefore, it needs a pull-up resistor from the v dd line to the sda pin. except for start and stop conditions, the data on the sda pin must be stable during the high period of the clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 5.0 ?i 2 c serial interface? for more details of i 2 c serial interface communication. 3.5 serial clock pin (scl) scl is the serial clock pin of the i 2 c interface. the mcp47x6 devices act only as a slave and the scl pin accepts only external serial clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock and output from the device occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs a pull-up resistor from the v dd line to the scl pin. refer to section 5.0 ?i 2 c serial interface? for more details of i 2 c serial interface communication. 3.6 voltage reference pin (v ref ) this pin is used for the external voltage reference input. the user can select v dd voltage or the v ref pin voltage as the reference resistor ladder?s voltage reference. when the v ref pin signal is selected, there is an option for this voltage to be buffered or unbuffered. this is offered in cases where the reference voltage does not have the current capability not to drop its voltage when connected to the internal resistor ladder circuit. when the v dd is selected as reference voltage, this pin is disconnected from the internal circuit. see section 4.2 ?dac?s (resistor ladder) reference voltage? and ta b l e 4 - 4 for more details on the configuration bits. 3.7 exposed pad (ep) this pad is conductively connected to the device's substrate. this pad should be tied to the same potential as the v ss pin (or left unconnected). this pad could be used to assist as a heat sink for the device when connected to a pcb heat sink.
? 2011 microchip technology inc. ds22272b-page 35 mcp4706/4716/4726 4.0 general description the mcp4706, mcp4716, and mcp4726 devices are single channel voltage output 8-bit, 10-bit, and 12-bit dac devices with nonvolatile memory (eeprom) and an i 2 c serial interface. this family will be referred to as mcp47x6. the devices use a resistor ladder architecture. the resistor ladder dac is driven from a software selectable voltage reference source. the source can be either the device?s internal v dd or the external v ref pin voltage. the dac output is buffered with a low power and precision output amplifier (op amp). this output amplifier provides a rail-to-rail output with low offset voltage and low noise. the gain of the output buffer is software configurable. this device also has user programmable nonvolatile memory (eeprom), which allows the user to save the desired por/bor value of the dac register and device configuration bits. the devices use a two-wire i 2 c serial communication interface and operate with a single supply voltage from 2.7v to 5.5v. 4.1 power-on reset/brown-out reset (por/bor) the internal power-on reset (por)/brown-out reset (bor) circuit monitors the power supply voltage (v dd ) during operation. this circuit ensures correct device start-up at system power-up and power-down events. v ram is the ram retention voltage and is always lower than the por trip point voltage. por occurs as the voltage is rising (typically from 0v), while bor occurs as the voltage is falling (typically from v dd(min) or higher). when the rising v dd voltage crosses the v por trip point, the following occurs: ? nonvolatile dac register value latched into volatile dac register ? nonvolatile configuration bit values latched into volatile configuration bits ? por status bit is set (? 1 ?) ? the reset delay timer starts; when timer times out (t pord ), the i 2 c interface is operational. the analog output (v out ) state will be determined by the state of the volatile configuration bits and the dac register. this is called a por reset (event). when the falling v dd voltage crosses the v por trip point, the following occurs: ? device is forced into a power-down state (pd1:pd0 = 11 ). analog circuitry is turned off. ? volatile dac register is forced to 000h ? volatile configuration bits v ref1 , v ref0 and g are forced to ? 0 ? figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. figure 4-1: power-on reset operation. v por t pord v dd(min ) normal operation bor reset, volatile dac register = 000h volatile vref1:vref0 = 00 device in below v ram device in por state unknown state minimum operating voltage device in unknown state device in power down state (60 s max.) volatile g = 0 volatile pd1:pd0 = 11 v bor volatile memory retains data value volatile memory becomes corrupted por starts reset delay timer. when timer times out, i 2 c? interface can operate (if v dd >= v dd(min) ) eeprom data latched into volatile configuration bits and dac register. por status bit is set (? 1 ?) por reset forced active
mcp4706/4716/4726 ds22272b-page 36 ? 2011 microchip technology inc. 4.2 dac?s (resistor ladder) reference voltage the device can be configured to use one of three voltage sources for the resistor ladder?s reference voltage (v rl ) (see figure 4-2 ). these are: 1. v dd pin voltage 2. v ref pin voltage internally buffered 3. v ref pin voltage unbuffered the selection of the voltage is specified with the volatile v ref1 :v ref0 configuration bits (see table 4-4 ). there are nonvolatile and volatile v ref1 :v ref0 configuration bits. on a por/bor event, the state of the nonvolatile v ref1 :v ref0 configuration bits are latched into the volatile v ref1 :v ref0 configuration bits. when the user selects the v dd as reference, the v ref pin voltage is not connected to the resistor ladder. if the v ref pin is selected, then one needs to select between the buffered or unbuffered mode. in unbuffered mode, the v ref pin voltage may be from v ss to v dd . in buffered mode, the v ref pin voltage may be from 0.01v to v dd -0.04v. the input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and frequency response. figure 4-2: resistor ladder reference voltage selection block diagram. 4.3 resistor ladder the resistor ladder is a digital potentiometer with the b terminal internally grounded and the a terminal connected to the selected reference voltage (see figure 4-3 ). the volatile dac register controls the wiper position. the wiper voltage (v w ) is proportional to the dac register value divided by the number of resistor elements (r s ) in the ladder (256, 1024, or 4096) related to the v rl voltage. the resistor ladder (r rl ) has a typical impedance of approximately 210 k ? . this resistor ladder resistance (r rl ) may vary from device to device up to 20%. since this is a voltage divider configuration, the actual r rl resistance does not effect the output given a fixed voltage at v rl . if the unbuffered v ref pin is used as the v rl voltage source, this voltage source should have a low output impedance. when the dac is powered down, the resistor ladder is disconnected from the selected reference voltage. figure 4-3: resistor ladder. note: in unbuffered mode, the voltage source should have a low output impedance. if the voltage source has a high output impedance, then the voltage on the v ref ?s pin would be lower than expected. the resistor ladder has a typical impedance of 210 k ? and a typical capacitance of 29 pf. note: any variation or noises on the reference source can directly affect the dac output. the reference voltage needs to be as clean as possible for accurate dac performance. v rl v dd buffer reference v ref1 :v ref0 selection v ref note: the maximum wiper position is 2 n - 1, while the number of resistors in the resistor ladder is 2 n . this means that when the dac register is at full scale, there is one resistor element (r s ) between the wiper and the v rl voltage. r s(2 n ) r s(2 n - 1) r s(2 n - 2) r s(1) 2 n - 1 2 n - 2 1 0 r rl v rl v w dac register v w = * v rl dac register value # resistors in resistor ladder where: # resistors in resistor ladder = 256 (mcp4706) 1024 (mcp4716) 4096 (mcp4726) pd1:pd0
? 2011 microchip technology inc. ds22272b-page 37 mcp4706/4716/4726 4.4 output buffer/v out operation the dac output is buffered with a low power and precision output amplifier (op amp). figure 4-4 shows a block diagram. this amplifier provides a rail-to-rail output with low offset voltage and low noise. the user can select the output gain of the output amplifier. gain options are: a) gain of 1, with either v dd or v ref pin used as reference voltage b) gain of 2, only when v ref pin is used as reference voltage. the v ref pin voltage should be limited to v dd /2. the amplifier?s output can drive the resistive and high capacitive loads without oscillation. the amplifier provides a maximum load current which is enough for most programmable voltage reference applications. refer to section 1.0 ?electrical characteristics? for the specifications of the output amplifier. in any of the three power-down modes, the op amp is powered down and its output becomes a high- impedance to the v out pin. figure 4-4: output buffer block diagram. 4.4.1 programmable gain the amplifier?s gain is controlled by the gain (g) con- figuration bit (see table 4-4 ) and the v rl reference selection. when the v rl reference selection is the device?s v dd voltage, the g bit is ignored and a gain of 1 is used. the volatile g bit value can be modified by: ? por event ? bor event ?i 2 c write commands ?i 2 c general call reset command 4.4.2 output voltage the volatile dac register?s value controls the analog v out voltage, along with the device?s five configuration bits. the volatile dac register?s value is unsigned binary. the formula for the output voltage is given in equation 4-1 . table 4-1 shows examples of volatile dac register values and the corresponding theoretical v out voltage for the mcp47x6 devices. equation 4-1: calculating output voltage (v out ) the dac register value will be latched on the falling edge of the acknowledge pulse of the write com- mand?s last byte. then the v out voltage will start driv- ing to the new value. the following events update the analog voltage output (v out ): ? power-on reset or general call reset command: output is updated with eeprom data. ? falling edge of the acknowledge pulse of the last write command byte. 4.4.2.1 resolution/step voltage the step voltage is dependent on the device resolution and the output voltage range. one lsb is defined as the ideal voltage difference between two successive codes. the step voltage can easily be calculated by using equation 4-1 where the dac register value is equal to 1. 4.4.3 driving resistive and capacitive loads the v out pin can drive up to 100 pf of capacitive load in parallel with a 5 k ? resistive load (to meet electrical specifications). figure 2-94 shows the v out vs. resistive load. v out drops slowly as the load resistance decreases after about 3.5 k ? . it is recommended to use a load with r l greater than 5 k ? . note: the load resistance must keep higher than 5 k ? for the stable and expected analog output (to meet electrical specifications). v out op amp gain (1x or 2x) (g = 0 or 1) v w note: when gain = 2 (v rl = v ref ), if v ref > v dd /2, the v out voltage will be limited to v dd . so if v ref = v dd , then the v out voltage will not change for volatile dac register values mid-scale and greater, since the op amp at full scale output. v out = * gain v rl * dac register value # resistors in resistor ladder # resistors in resistor ladder = 4096 (mcp4726) 1024 (mcp4716) 256 (mcp4706)
mcp4706/4716/4726 ds22272b-page 38 ? 2011 microchip technology inc. table 4-1: dac input code vs. analog output (v out ) (v dd = 5.0v) device volatile dac register value v rl (1) lsb gain selection (2) v out (4) equation uv equation v mcp4726 (12-bit) 1111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl * (4095/4096) * 1 4.998779 2.5v 2.5v/4096 610.4 1x v rl * (4095/4096) * 1 2.499390 2x (3) v rl * (4095/4096) * 2) 4.998779 0111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl * (2047/4096) * 1) 2.498779 2.5v 2.5v/4096 610.4 1x v rl * (2047/4096) * 1) 1.249390 2x (3) v rl * (2047/4096) * 2) 2.498779 0011 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl * (1023/4096) * 1) 1.248779 2.5v 2.5v/4096 610.4 1x v rl * (1023/4096) * 1) 0.624390 2x (3) v rl * (1023/4096) * 2) 1.248779 0000 0000 0000 5.0v 5.0v/4096 1,220.7 1x v rl * (0/4096) * 1) 0 2.5v 2.5v/4096 610.4 1x v rl * (0/4096) * 1) 0 2x (3) v rl * (0/4096) * 2) 0 mcp4716 (10-bit) 11 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl * (1023/1024) * 1 4.995117 2.5v 2.5v/1024 2,441.4 1x v rl * (1023/1024) * 1 2.497559 2x (3) v rl * (1023/1024) * 2 4.995117 01 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl * (511/1024) * 1 2.495117 2.5v 2.5v/1024 2,441.4 1x v rl * (511/1024) * 1 1.247559 2x (3) v rl * (511/1024) * 2 2.495117 00 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl * (255/1024) * 1 1.245117 2.5v 2.5v/1024 2,441.4 1x v rl * (255/1024) * 1 0.622559 2x (3) v rl * (255/1024) * 2 1.245117 00 0000 0000 5.0v 5.0v/1024 4,882.8 1x v rl * (0/1024) * 1 0 2.5v 2.5v/1024 2,441.4 1x v rl * (0/1024) * 1 0 2x (3) v rl * (0/1024) * 1 0 mcp4706 (8-bit) 1111 1111 5.0v 5.0v/256 19,531.3 1x v rl * (255/256) * 1 4.980469 2.5v 2.5v/256 9,765.6 1x v rl * (255/256) * 1 2.490234 2x (3) v rl * (255/256) * 2 4.980469 0111 1111 5.0v 5.0v/256 19,531.3 1x v rl * (127/256) * 1 2.480469 2.5v 2.5v/256 9,765.6 1x v rl * (127/256) * 1 1.240234 2x (3) v rl * (127/256) * 2 2.480469 0011 1111 5.0v 5.0v/256 19,531.3 1x v rl * (63/256) * 1 1.230469 2.5v 2.5v/256 9,765.6 1x v rl * (63/256) * 1 0.615234 2x (3) v rl * (63/256) * 2 1.230469 0000 0000 5.0v 5.0v/256 19,531.3 1x v rl * (0/256) * 1 0 2.5v 2.5v/256 9,765.6 1x v rl * (0/256) * 1 0 2x (3) v rl * (0/256) * 2 0 note 1: v rl is the resistor ladder?s reference voltage. it is independent of v ref1 :v ref0 selection. 2: gain selection of 2x requires voltage reference source to come from v ref pin and requires v ref pin voltage ? v dd / 2. 3: requires g = 1 , v ref1 :v ref0 = 10 or ? 11 ?, and v rl ? v dd /2. 4: these theoretical calculations do not take into account the offset and gain errors.
? 2011 microchip technology inc. ds22272b-page 39 mcp4706/4716/4726 4.5 power-down operation to allow the application to conserve power when the dac operation is not required, three power-down modes are available. the power-down configuration bits (pd1:pd0) control the power-down operation ( figure 4-5 ). all power-down modes do the following: ? turning off most of its internal circuits (op amp, resistor ladder, ...) ? op amp output becomes high-impedance to the v out pin ? disconnects resistor ladder from reference voltage (v rl ) ? retains the value of the volatile dac register and configuration bits, and the nonvolatile (eeprom) dac register and configuration bits depending on the selected power-down mode, the following will occur: ?v out pin is switched to one of three resistive pull- downs (see tab le 4 -2 ) - 640k ? (typical) - 125k ? (typical) -1k ? (typical) there is a delay (t pde ) between the pd1:pd0 bits changing from ? 00 ? to either ? 01 ?, ? 10 ?, or ? 11 ? and the op amp no longer driving the v out output and the pull- down resistors are sinking current. in any of the power-down modes, where the v out pin is not externally connected (sinking or sourcing current), the power-down current will typical be 60 na (see section 1.0 ?electrical characteristics? ) . section 6.0 ?mcp47x6 i2c commands? describes the i 2 c commands for writing the power-down bits. the commands that can update the volatile pd1:pd0 bits are: ? write volatile dac register ? write volatile memory ? write all memory ? write volatile configuration bits ? general call reset ? general call wake-up table 4-2: power-down bits and output resistive load figure 4-5: op amp to v out pin block diagram. 4.5.1 exiting power-down when the device exits the power-down mode the following occurs: ? disabled circuits (op amp, resistor ladder, ...) are turned on ? resistor ladder is connected to selected reference voltage (v rl ) ? selected pull-down resistor is disconnected ?the v out output will be driven to the voltage represented by the volatile dac register?s value and configuration bits the v out output signal will require time as these circuits are powered up and the output voltage is driven to the specified value as determined by the volatile dac register and configuration bits. the following events will change the pd1:pd0 bits to ? 00 ? and therefore exit the power-down mode. these are: ?any i 2 c write command for where the pd1:pd0 bits are ? 00 ?. ?i 2 c general call wake-up command. ?i 2 c general call reset command. (if nonvolatile pd1:pd0 bits are ? 00 ?). note: the i 2 c serial interface circuit is not affected by the power-down mode. this circuit remains active in order to receive any command that might come from the i 2 c master device. pd1 pd0 function 00 normal operation 01 1k ? resistor to ground 10 125 k ? resistor to ground 11 640 k ? resistor to ground note: since the op amp and resistor ladder were powered off (0v), the op amp?s input voltage (v w ) can be considered 0v. there is a delay (t pdd ) between the pd1:pd0 bits updated to ? 00 ? and the op amp driving the v out output. the op amp?s settling time (from 0v) needs to be taken into account to ensure the v out voltage reflects the selected value. v out pd1:pd0 op amp 1k ? 125 k ? 640 k ? gain (1x or 2x) (gx = 0 or 1 ) v w
mcp4706/4716/4726 ds22272b-page 40 ? 2011 microchip technology inc. 4.6 device resets device resets can be grouped into two types. resets due to change in voltage (por/bor reset), and resets caused by the system master (such as a microcontroller). after a device reset, and when v dd ? v dd(min) , the device memory may be written or read. 4.6.1 por/bor reset operation the por and bor trip points are at the same voltage, and is determined if the v dd voltage is rising or falling (see figure 4-1 ). what occurs is different depending if the reset is a por or bor reset. por reset (v dd rising) on a por reset, the nonvolatile memory values (dac register and configuration bits) are latched into the vol- atile memory. this configures the analog output (v out ) circuitry. also a reset delay timer starts. during this delay time, the i 2 c interface will not accept commands. bor reset (v dd falling) on a bor reset, the device is forced into a power- down state. the volatile pd1:pd0 bits forced to ? 11 ? and all other volatile memory forced to ? 0 ?. the i 2 c interface will not accept commands. 4.6.2 reset commands when the mcp47x6 is in the valid operating voltage, the i 2 c general call reset command will force a reset event. this is similar to the por reset, except that the reset delay timer is not started. in the case where the i 2 c interface bus does not seem to be responsive, the technique shown in section 8.9, software i2c interface reset sequence can be used to force the i 2 c interface to be reset. 4.7 dac registers, configuration bits, and status bits the mcp47x6 devices have both volatile and nonvolatile (eeprom) memory. figure 4-6 shows the volatile and nonvolatile memory and their interaction due to a por event. there are five configuration bits in both the volatile and nonvolatile memory, the dac registers in both the volatile and nonvolatile memory, and two volatile status bits. the dac registers (volatile and nonvolatile) will be either 12-bits (mcp4726), 10-bits (mcp4716), or 8-bits (mcp4706) wide. when the device is first powered up, it automatically uploads the eeprom memory values to the volatile memory. the volatile memory determines the analog output (v out ) pin voltage. after the device is powered up, the user can update the device memory. the i 2 c interface is how this memory is read and written. refer to section 5.0 ?i 2 c serial interface? and section 6.0 ?mcp47x6 i2c commands? for more details on the reading and writing the device?s memory. when the nonvolatile memory is written (using the i 2 c write all memory command), the volatile memory is written with the same values. the device starts writing the eeprom cell at the acknowledge pulse of the eeprom write command. tab l e 4 - 3 shows the operation of the device status bits, tab l e 4 - 4 shows the operation of the device configura- tion bits, and table 4-5 shows the factory default value of a por/bor event for the device configuration bits. there are two status bits. these are only in volatile memory and give indication on the status of the device. the por bit indicates if the device v dd is above or below the por trip point. during normal operation, this bit should be ? 1 ?. the rdy/bsy bit indicates if an eeprom write cycle is in progress. while the rdy/ bsy bit is low (during the eeprom writing), all commands are ignored, except for the read command. figure 4-6: dac memory and por interaction. v ref1 dac register value (1) n.v. memory config bits vol. memory por event v ref0 pd1 pd0 g v ref1 v ref0 pd1 pd0 g rdy/bsy por status bits (2) d max d 1 d 0 d max d 1 d 0 note 1: the d max value depends on the device. for the mcp4706: d max = d 7 , mcp4716: d max = d 9 , and the mcp4726: d max = d 11 . 2: status bits are read-only.
? 2011 microchip technology inc. ds22272b-page 41 mcp4706/4716/4726 table 4-3: status bits operation table 4-4: configurat ion bits table 4-5: configuration bit valu es after por/bor event register 4-1: dac register bits name function rdy/bsy this bit indicates the state of the eeprom program memory 1 = eeprom is not in a programming cycle 0 = eeprom is in a programming cycle por power-on reset status indicator (flag) 1 = device is powered on with v dd > v por . ensure that v dd is above v dd(min) to ensure proper operation. 0 = device is in powered off state. if this value is read, v dd < v dd(min) < v por . unreliable device operation should be expected. name function v ref 1:v ref 0 resistor ladder voltage reference (v rl ) selection bits 0x =v dd (unbuffered) 10 =v ref pin (unbuffered) 11 =v ref pin (buffered) pd1:pd0 power-down selection bits when the dac is powered down, most of the internal circuits are powered off and the op amp is disconnected from the v out pin. 00 = not powered down (normal operation) 01 = powered down ? v out is loaded with 1 k ? resistor to ground. 10 = powered down ? v out is loaded with 100 k ? resistor to ground. 11 = powered down ? v out is loaded with 500 k ? resistor to ground. note: see tab l e 4 - 2 and figure 4-5 for more details. g gain selection bit 0 = 1x (gain of 1) 1 = 2x (gain of 2). not applicable when v dd is used as v rl note: if v ref = v dd , the device uses a gain of 1 only, regardless of the gain selection bit (g) setting. r/w r/w r/w r/w r/w comment bit name vref1 vref0 pd1 pd0 g por event 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) when v dd transitions from v dd < v por to v dd > v por bor event 00110 when v dd transitions from v dd > v bor to v dd < v bor note 1: default configuration when the device is shipped to customer. the por/bor value may be modified by writing the corresponding nonvolatile configuration bit. r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w comment bit name ? (2) ? (2) ? (2) ? (2) d7 d6 d5 d4 d3 d2 d1 d0 mcp4706 ? (2) ? (2) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mcp4716 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mcp4726 por/bor event 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) note 1: default configuration when the device is shipped to customer. the por/bor value may be modified by writing the corresponding nonvolatile configuration bit. 2: this device does not implement this bit, so there is no corresponding por/bor value.
mcp4706/4716/4726 ds22272b-page 42 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22272b-page 43 mcp4706/4716/4726 5.0 i 2 c serial interface the mcp47x6 devices support the i 2 c serial protocol. the mcp47x6 i 2 c?s module operates in slave mode (does not generate the serial clock). 5.1 overview this i 2 c interface is a two-wire interface. figure 5-1 shows a typical i 2 c interface connection. the i 2 c interface specifies different communication bit rates. these are referred to as standard, fast or high- speed modes. the mcp47x6 supports these three modes. the bit rates of these modes are: ? standard mode: bit rates up to 100 kbit/s ? fast mode: bit rates up to 400 kbit/s ? high-speed mode (hs mode): bit rates up to 3.4 mbit/s a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mcp47x6 device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communication is initiated by the master (microcontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the r/w bit. figure 5-1: typical i 2 c interface. the i 2 c serial protocol only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. for details on the frame content (commands/data) refer to section 6.0 . refer to the nxp i 2 c document for more details on the i 2 c specifications. 5.2 signal descriptions the i 2 c interface uses up to two pins (signals). these are: ? sda (serial data) ? scl (serial clock) 5.2.1 serial data (sda) the serial data (sda) signal is the data signal of the device. the value on this pin is latched on the rising edge of the scl signal when the signal is an input. with the exception of the start and stop conditions, the high or low state of the sda pin can only change when the clock signal on the scl pin is low. during the high period of the clock, the sda pin?s value (high or low) must be stable. changes in the sda pin?s value while the scl pin is high will be interpreted as a start or a stop condition. 5.2.2 serial clock (scl) the serial clock (scl) signal is the clock signal of the device. the rising edge of the scl signal latches the value on the sda pin. the mcp47x6 will not stretch the clock signal (scl) since memory read access occurs fast enough. depending on the clock rate mode, the interface will display different characteristics. scl scl mcp4xxx sda sda host controller typical i 2 c? interface connections
mcp4706/4716/4726 ds22272b-page 44 ? 2011 microchip technology inc. 5.3 i 2 c operation the mcp47x6?s i 2 c module is compatible with the nxp i 2 c specification. the following lists some of the module?s features: ? 7-bit slave addressing ? supports three clock rate modes: - standard mode, clock rates up to 100 khz - fast mode, clock rates up to 400 khz - high-speed mode (hs mode), clock rates up to 3.4 mhz ? support multi-master applications ? general call addressing (reset and wake-up commands) the i 2 c 10-bit addressing mode is not supported. the nxp i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content for the mcp47x6 is defined in section 6.0 . 5.3.1 i 2 c bit states and sequence figure 5-8 shows the i 2 c transfer sequence. the serial clock is generated by the master. the following definitions are used for the bit states: ? start bit (s) ? data bit ? acknowledge (a) bit (driven low) / no acknowledge (a ) bit (not driven low) ? repeated start bit (sr) ? stop bit (p) 5.3.1.1 start bit the start bit (see figure 5-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is ?high?. figure 5-2: start bit. 5.3.1.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 5-3 ). figure 5-3: data bit. 5.3.1.3 acknowledge (a) bit the a bit (see figure 5-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the a bit may indicate different things. typically, the slave device will supply an a response after the start bit and 8 ?data? bits have been received. an a bit has the sda signal low. figure 5-4: acknowledge waveform. not a (a ) response the a bit has the sda signal high. table 5-1 shows some of the conditions where the slave device will issue a not a (a ). if an error condition occurs (such as an a instead of a), then a start bit must be issued to reset the command state machine. table 5-1: mcp47x6 a/a responses sda scl s 1st bit 2nd bit sda scl data bit 1st bit 2nd bit event acknowledge bit response comment general call a slave address valid a slave address not valid a communication during eeprom write cycle a after device has received address and command, and valid conditions for eeprom write bus collision n/a i 2 c module resets, or a ?don?t care? if the collision occurs on the master?s ?start bit? a 8 d0 9 sda scl
? 2011 microchip technology inc. ds22272b-page 45 mcp4706/4716/4726 5.3.1.4 repeated start bit the repeated start bit (see figure 5-5 ) indicates the current master device wishes to continue communicating with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is ?high?. figure 5-5: repeat start condition waveform. 5.3.1.5 stop bit the stop bit (see figure 5-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is ?high?. a stop bit resets the i 2 c interface of all mcp47x6 devices. figure 5-6: stop condition receive or transmit mode. 5.3.2 clock stretching ?clock stretching? is something that the receiving device can do, to allow additional time to ?respond? to the ?data? that has been received. the mcp47x6 will not stretch the clock signal (scl) since memory read access occurs fast enough. 5.3.3 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure 5-7: typical 8-bit i 2 c waveform format. figure 5-8: i 2 c data states and bit sequence. note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data " 1 ". sda scl sr = repeated start 1st bit scl sda a / a p 1st bit sda scl s 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit p a / a scl sda start condition stop condition data allowed to change data or a valid
mcp4706/4716/4726 ds22272b-page 46 ? 2011 microchip technology inc. 5.3.4 slope control the mcp47x6 implements slope control on the sda output. as the device transitions from hs mode to fs mode, the slope control parameter will change from the hs specification to the fs specification. for fast (fs) and high-speed (hs) modes, the device has a spike suppression and a schmidt trigger at sda and scl inputs. 5.3.5 device addressing the address byte is the first byte received following the start condition from the master device. the mcp47x6?s slave address consists of a 4-bit fixed code (? 1100 ?) and a 3-bit code that is user specified when the device is ordered. this allows up to eight mcp47x6 devices on a single i 2 c bus. figure 5-9 shows the i 2 c slave address byte format, which contains the seven address bits and a read/write (r/w ) bit. tab l e 5 - 2 shows the eight i 2 c slave address options and their respective device order code. figure 5-9: slave address bits in the i 2 c control byte. table 5-2: i 2 c address/order code start bit read/write bit address byte r/w ack acknowledge bit slave address 1 1 0 0 slave address (7-bits) a2 a1 a0 note: address bits (a2:a0) specified at time of device order, see table 5-2 . fixed user specified 7-bit i 2 c? address device order code comment ? 1100000 ? mcp47x6a0-e/xx mcp47x6a0t-e/xx tape and reel ? 1100001 ? mcp47x6a1-e/xx mcp47x6a1t-e/xx tape and reel ? 1100010 ? mcp47x6a2-e/xx mcp47x6a2t-e/xx tape and reel ? 1100011 ? mcp47x6a3-e/xx mcp47x6a3t-e/xx tape and reel ? 1100100 ? mcp47x6a4-e/xx mcp47x6a4t-e/xx tape and reel ? 1100101 ? mcp47x6a5-e/xx mcp47x6a5t-e/xx tape and reel ? 1100110 ? mcp47x6a6-e/xx mcp47x6a6t-e/xx tape and reel ? 1100111 ? mcp47x6a7-e/xx mcp47x6a7t-e/xx tape and reel note 1: the sample center will generally stock i 2 c address ? 1100000 ?, other addresses may be available. 2: ? xx ? in the order code is the device package code (ch for sot-23 and ma for dfn)
? 2011 microchip technology inc. ds22272b-page 47 mcp4706/4716/4726 5.3.6 hs mode the i 2 c specification requires that a high-speed mode device must be ?activated? to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the mcp47x6 device does not acknowledge this byte. however, upon receiving this command, the device switches to hs mode. the device can now communicate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. the master device can then either issue a repeated start bit to address a different device (at high-speed) or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. see figure 5-10 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the nxp i 2 c specification. 5.3.6.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. 5.3.6.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes < 10 ns during hs mode. figure 5-10: hs mode sequence. s a ? 0 0 0 0 1 x x x ?b sr a ?slave address? a /a ?data? p s = start bit sr = repeated start bit a = acknowledge bit a = not acknowledge bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs mode hs mode continues f/s mode sr a ?slave address? r/w hs select byte control byte command/data byte(s) control byte
mcp4706/4716/4726 ds22272b-page 48 ? 2011 microchip technology inc. 5.3.7 general call the general call is a method that the ?master? device can communicate with all other ?slave? devices. in a multi-master application, the other master devices are operating in slave mode. the general call address has two documented formats. these are shown in figure 5-11 . the mcp47x6 has two general call commands. the function of these commands are: ? reset the device(s) (software reset) ? wake-up the device(s) for details on the operation of the mcp47x6?s general call commands, see section 6.6 . figure 5-11: general call formats. note: only one general call command per issue of the general call control byte. any additional general call commands are ignored and not acknowledged. 0 000 s 0000 x xxxx a xx0 ap general call address second byte ?7-bit command? reserved 7-bit commands (by i 2 c specification ? nxp specification # um10204, rev. 03 19 june 2007) ?0000 011? b - reset and write programmable part of slave address by hardware. ?0000 010? b - write programmable part of slave address by hardware. ?0000 000? b - not allowed the following is a ?hardware general call? format 0 000 s 0000 x xxxx a xx1 a general call address second byte ?master address? x xxxx xxx ap n occurrences of (data + a) this indicates a ?hardware general call?
? 2011 microchip technology inc. ds22272b-page 49 mcp4706/4716/4726 6.0 mcp47x6 i 2 c commands the i 2 c protocol does not specify how commands are formatted, so this section specifies the mcp47x6?s i 2 c command formats and operation. the commands can be grouped into the following categories: ? write memory ? read memory ? general call commands the supported commands are shown in table 6-2 . many of these commands allow for continuous operation. this means that the i 2 c master does not generate a stop bit but repeats the required data/ clocks. this allows faster updates since the overhead of the i 2 c control byte is removed. table 6-1 shows the supported commands and the required number of bit clocks for both single and continuous commands. write commands, determined by the r/w bit = 0 , use up to three command codes bits (c2:c0) to determine the write?s operation. the read command is strictly determined by the r/w bit = 1 . there are two formats of the command. one for 12-bit and 10-bit devices and a second for 8-bit devices. the general call commands utilize the i 2 c specification reserved general call command address and command codes. table 6-1: i 2 c commands - number of clocks 6.0.1 aborting a transmission a restart or stop condition in an expected data bit position will abort the current command sequence and data will not be written to the mcp47x6. table 6-2: mcp47x6 supported commands command # of bit clocks ( 1 ) operation mode write volatile dac register command (2) single 29 continuous 18n + 11 write volatile memory command single 38 continuous 27n + 11 write all memory command single 38 continuous 27n + 11 write volatile configuration bits command single 20 continuous 9n + 11 read command (12 and 10-bit dac register) (2) single 65 continuous 54n + 11 read command (8-bit dac register) (2) single 47 continuous 36n + 11 note 1: ?n? indicates the number of times the command operation is to be repeated. 2: this command is useful to determine when an eeprom programming cycle has completed (rdy/bsy status bit) command code ( note 1 ) command name writes volatile memory? writes eeprom memory? command during eeprom write cycle? comment c2 c1 c0 config. dac config. dac 00x write volatile dac register command ( note 2 ) pd1:pd 0 only yes no no no writes volatile power- down bits so can also be used to exit a power-down state. 010 write volatile memory command yes yes no no no 011 write all memory command yes yes yes yes no 100 write volatile configuration bits command yes no no no no 101 reserved n/a n/a n/a n/a n/a reserved ( note 3 ) 110 111 n/a n/a n/a n/a reserved ( note 3 ) n/a read command n/a n/a n/a n/a yes determined by r/w bit in i 2 c? control byte general call reset n/a n/a n/a n/a no determined by general call command byte after the i 2 c general call address. general call wake-up n/a n/a n/a n/a no note 1: these bits are the msb of the 2nd byte in the i 2 c write command. see figure 6-1 to figure 6-4 . 2: x = don?t care bit. this command format does not use c0 bit. 3: device operation is not specified.
mcp4706/4716/4726 ds22272b-page 50 ? 2011 microchip technology inc. 6.1 write volatile dac register (c2:c0 = 00x ) this command is used to update the volatile dac register value and the two power-down configuration bits (pd1:pd0). this command is typically used for a quick update of the analog output by modifying the minimum parameters. the eeprom values are not affected by this command. figure 6-1 shows an example of the command format, where a stop bit completes the command. the volatile dac register and power-down configura- tion bits are updated with the written date at the com- pletion of the ack bit (falling edge of scl). after this ack bit, the i 2 c master should generate a stop bit or the i 2 c master can repeat the 2nd (2 command bits + 2 power-down bits + 4 data bits (b11:b08)) and the 3rd byte (8 data bits (b07:b00)). repeating the 2nd and 3rd bytes allows a continuous command where the volatile dac register can be updated without the communication overhead of the device addressing byte (1st byte). the device updates the v out at the falling edge of the acknowledge pulse of the 3rd byte. figure 6-1: write volatile dac register command. device addressing data bits (8 bits) note 1: the device updates v out at the falling edge of the scl at the end of this ack pulse. note 1 2: the 2nd-3rd bytes can be repeated after the 3rd byte by continued clocking before issuing stop bit. command 3: ack bit generated by mcp47x6 . note 2 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 mcp4726 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 mcp4716 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 x x mcp4706 x x x x d07 d06 d05 d04 d03 d02 d01 d00 sda scl a2 a1 a0 1100 0000 pd1 pd0 b11 b10 b09 b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0 data bits (4 bits) data bits (12 bits) start bit ack bit (3) read/write bit (write) stop bit s a r/w a a p power bits down bits ack bit (3) ack bit (3) legend: x = don?t care d11:d00 = 12-bit data for mcp4726 device d09:d00 = 10-bit data for mcp4716 device d07:d00 = 8-bit data for mcp4706 device
? 2011 microchip technology inc. ds22272b-page 51 mcp4706/4716/4726 6.2 write volatile memory (c2:c0 = 010 ) this write command is used to update the volatile dac register value and configuration bits. the eeprom is not affected by this command. figure 6-2 shows an example of this write command. the volatile dac register and configuration bits are updated with the written date at the completion of the ack bit (falling edge of scl). after this ack bit, the i 2 c master should generate a stop bit or the i 2 c master can repeat the 2nd (3 command bits + 5 configuration bits), and the 3rd byte (8 data bits (b15:b08)), and the 4th byte (8 data bits (b07:b00)). repeating the 2nd through 4th bytes allows a continuous command where the volatile dac register and configuration bits can be updated without the communication overhead of the device addressing byte (1st byte). figure 6-2: write volatile memory command. device addressing data bits (8 bits) (3rd byte) note 1: the device updates v out at the falling edge of the scl at the end of this ack pulse. note 1 2: the 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing stop bit. command 3: ack bit generated by mcp47x6 . note 2 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 mcp4726 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 x x x x mcp4716 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 x x x x x x mcp4706 d07 d06 d05 d04 d03 d02 d01 d00 x x x x x x x x sda scl a2 a1 a0 1100 0001 pd1 pd0 g 0 b15 b14 b13 b12 b11 b10 b09 b08 0 ref. data bits (16 bits) (3rd + 4th bytes) start bit ack bit (3) read/write bit (write) stop bit s a r/w a a power- bits down bits ack bit (3) ack bit (3) legend: x = don?t care d11:d00 = 12-bit data for mcp4726 device d09:d00 = 10-bit data for mcp4716 device d07:d00 = 8-bit data for mcp4706 device 0 vref1 vref0 data bits (8 bits) (4th byte) b07 b06 b05 b04 b03 b02 b01 b00 0 a p ack bit (3) voltage select bits gain bit
mcp4706/4716/4726 ds22272b-page 52 ? 2011 microchip technology inc. 6.3 write all memory (c2:c0 = 011 ) this write command is used to update the volatile and nonvolatile (eeprom) dac register value and config- uration bits. figure 6-3 shows an example of this write command. ?v out update: at the falling edge of the acknowledge pulse of the 4th byte. ? eeprom update: at the falling edge of the acknowledge pulse of the 4th byte. the dac register and power-down configuration bits (volatile and eeprom) are updated with the written date at the completion of the ack bit (falling edge of scl). the eeprom memory requires time (t wc ) for the values to be written. another write all memory command should not be issued until the eeprom write is complete. write commands which only update volatile memory (c2:c0 = 00x or ? 010 ?) can be issued. read commands and the general call commands may not be issued. figure 6-3: write all memory command. note: rdy/bsy bit toggles to ?low? and back to ?high? after the eeprom write is completed. the state of the rdy/bsy bit can be monitored by a read command. device addressing data bits (8 bits) (3rd byte) note 1: the device updates v out at the falling edge of the scl at the end of this ack pulse. note 1 2: the 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing stop bit. command 3: ack bit generated by mcp47x6. note 2 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 mcp4726 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 x x x x mcp4716 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 x x x x x x mcp4706 d07 d06 d05 d04 d03 d02 d01 d00 x x x x x x x x sda scl a2 a1 a0 1100 0001 pd1 pd0 g 0 b15 b14 b13 b12 b11 b10 b09 b08 0 ref. data bits (16 bits) (3rd + 4th bytes) start bit ack bit (3) read/write bit (write) stop bit s a r/w a a power- bits down bits ack bit (3) ack bit (3) legend: x = don?t care d11:d00 = 12-bit data for mcp4726 device d09:d00 = 10-bit data for mcp4716 device d07:d00 = 8-bit data for mcp4706 device 1 vref1 vref0 data bits (8 bits) (4th byte) b07 b06 b05 b04 b03 b02 b01 b00 0 a p ack bit (3) voltage select bits gain bit
? 2011 microchip technology inc. ds22272b-page 53 mcp4706/4716/4726 6.4 write volatile configuration bits (c2:c0 = 100 ) this write command is used to update the volatile configuration register bits only. this command is a quick method to modify the configuration of the dac, such as the selection of the resistor ladder reference voltage, the op amp gain, and the power-down state. figure 6-4 shows an example of this write command. figure 6-4: write volatile configuration bits command. device addressing note 1: the device updates v out at the falling edge of the scl at the end of this ack pulse. note 1 2: the 2nd byte can be repeated after the 2nd by continued clocking before issuing stop bit. command 3: ack bit generated by mcp47x6. note 2 sda scl a2 a1 a0 1100 0010 pd1 pd0 g 0 configuration bits start bit ack bit (3) read/write bit (write) stop bit s a r/w a bits ack bit (3) 0 vref1 vref0 p
mcp4706/4716/4726 ds22272b-page 54 ? 2011 microchip technology inc. 6.5 read command this command reads all the device memory. this includes the volatile and nonvolatile (eeprom) dac register values and configuration bits, and the volatile status bits. this command is executed when the i 2 c control byte?s read/write bit is a ? 1 ? (read). this command has two different formats based on the resolution of the device. the 12-bit and 10-bit devices use the format in figure 6-5 , while the 8-bit device uses the format in figure 6-6 . the 2nd byte (configuration bits) indicates the current condition of the device operation. the rdy/bsy bit indicates eeprom writing status. figure 6-5: read command format for 12-bit dac (mcp4726) and 10-bit dac (mcp4716). device addressing note 1: the 2nd-7th bytes can be repeated after the 7th byte by continued clocking before issuing stop bit. 2: ack bit generated by mcp47x6. 3: ack bit generated by i 2 c master. b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 mcp4726 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 mcp4716 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 sda scl a2 a1 a0 1100 1 0 pd1 pd0 g data bits (16 bits) (3rd + 4th bytes, and 6th + 7th bytes) start bit ack bit (3) read/write bit (read) s a r/w legend: d11:d00 = 12-bit data for mcp4726 device d09:d00 = 10-bit data for mcp4716 device 0 vref1 vref0 a rdy por vol. data bits (8 bits) (4th byte) b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0 a 0 b15 b14 b13 b12 b11 b10 b09 a vol. data bits (8 bits) (3rd byte) ack bit (4) ack bit (4) note 1 stop bit a/n p ack/nack bit (5) nv data bits (8 bits) (7th byte) b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0 / 1 a 0 b15 b14 b13 b12 b11 b10 b09 a nv data bits (8 bits) (6th byte) ack bit (4) ack bit (4) ack bit (4) pd1 pd0 g 1 vref1 vref0 rdy por vol. vol. configuration status bits bits vol. nv configuration status bits bits 4: ack/nack bit generated by i 2 c master.
? 2011 microchip technology inc. ds22272b-page 55 mcp4706/4716/4726 figure 6-6: read command format for 8-bit dac (mcp4706). device addressing vol. data bits (8 bits) (3rd byte) note 1: note 1 the 2nd-5th bytes can be repeated after the 5th byte by continued clocking before issuing stop bit. vol. 2: ack bit generated by mcp47x6. b07 b06 b05 b04 b03 b02 b01 b00 mcp4706 d07 d06 d05 d04 d03 d02 d01 d00 sda scl a2 a1 a0 1100 1 0 pd1 pd0 g 0 b07 b06 b05 b04 b03 b02 b01 b00 0 vol. configuration data bits (8 bits) (3rd and 5th bytes) start bit ack bit (2) read/write bit (read) stop bit s a r/w a a status ack bit (3) ack bit (3) legend: d07:d00 = 8-bit data for mcp4706 device 0 vref1 vref0 a/n p ack/nack bit (4) rdy por nv data bits (8 bits) (5th byte) 0 b07 b06 b05 b04 b03 b02 b01 b00 0 / 1 a ack bit (3) pd1 pd0 g 1 vref1 vref0 rdy por vol. nv configuration status bits bits bits bits 3: ack bit generated by i 2 c? master. 4: ack/nack bit generated by i 2 c? master.
mcp4706/4716/4726 ds22272b-page 56 ? 2011 microchip technology inc. 6.6 i 2 c general call commands the device acknowledges the general call address command ( 0x00 in the first byte). the meaning of the general call address is always specified in the second byte. the i 2 c specification does not allow ? 00000000 ? (00h) in the second byte. please refer to the phillips i 2 c document for more details on the general call specifications. the mcp47x6 devices support the following i 2 c general calls: ? general call reset ? general call wake-up 6.6.1 general call reset the device performs general call reset if the second byte is ? 00000110 ? (06h). at the acknowledgement of this byte, the device will abort the current conversion and perform the following tasks: ? internal reset similar to a power-on reset (por). the contents of the eeprom are loaded into the dac registers and analog output is available immediately. ? this is a similar event to the por. the v out will be available immediately, but after a short time delay following the acknowledgement pulse. the v out value is determined by the eeprom contents. this command allows multiple mcp47x6 devices to be reset synchronously. figure 6-7: general call reset command. general call address note 1: at the falling edge of the scl at the end of this ack pulse a reset occurs (start-up timer starts and dac register note 1 2: the 2nd byte can be repeated after the 2nd by continued clocking before issuing stop bit. general call reset command 3: ack bit generated by mcp47x6. note 2 sda scl 000 0000 0000 0 start bit ack bit (3) read/write bit (write) stop bit s a r/w a ack bit (3) 0 p 00110 latched).
? 2011 microchip technology inc. ds22272b-page 57 mcp4706/4716/4726 6.6.2 general call wake-up if the second byte is ? 00001001 ? (09h), the device forces the volatile power-down bits to ? 00 ?. the nonvolatile (eeprom) power-down bit values are not affected by this command. this command allows multiple mcp47x6 devices to wake-up synchronously. figure 6-8: general call wake-up command. note: this command does not adhere to the i 2 c specification where if the lsb of the 2nd byte is a ? 1 ?, it is a ?hardware general call? (see the nxp i 2 c specification). general call address note 1: at the falling edge of the scl, at the end of this ack pulse, the volatile pd1:pd0 bits are forced to ? 00 ?. note 1 2: the 2nd byte can be repeated after the 2nd by continued clocking before issuing stop bit. general call wake-up 3: ack bit generated by mcp47x6. note 2 sda scl 000 0000 0000 0 start bit ack bit (3) read/write bit (write) stop bit s a r/w a ack bit (3) 0 p 01001 command
mcp4706/4716/4726 ds22272b-page 58 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22272b-page 59 mcp4706/4716/4726 7.0 terminology 7.1 resolution the resolution is the number of dac output states that divide the full-scale range. for the 12-bit dac, the resolution is 2 12 , meaning the dac code ranges from 0 to 4095. 7.2 least significant bit (lsb) normally this is thought of as the ideal voltage difference between two successive codes. this bit has the smallest value or weight of all bits in the register. for a given output voltage range, which is typically the voltage between the full-scale voltage and the zero- scale voltage (v out(fs) - v out(zs) ), it is divided by the resolution of the device ( equation 7-1 ). equation 7-1: lsb voltage calculation 7.3 monotonicity normally this is thought of as the v out voltage never decreasing, as the dac register code is continuously incremented by 1 code step (lsb). 7.4 full-scale error (fse) the full-scale error (see figure 7-4 ) is the sum of offset error plus gain error. it is the difference between the ideal and measured dac output voltage with all bits set to one (dac input code = fffh for 12-bit dac). equation 7-2: full-scale error 7.5 zero-scale error (zse) the zero-scale error (see figure 7-4 ) is the difference between the ideal and measured v out voltage with the volatile dac register equal to 000h. the zero-scale error is the same as the offset error for this case (volatile dac register = 000h). equation 7-3: zero-scale error 7.6 offset error the offset error (see figure 7-1 ) is the deviation from zero voltage output when the volatile dac register value = 000h (zero scale voltage). this error affects all codes by the same amount. the offset error can be calibrated by software in application circuits. figure 7-1: offset error example. v lsb = v out(fs) - v out(zs) 2 n - 1 2 n = 4096 (mcp4726) 1024 (mcp4716) 256 (mcp4706) fse = v out(@fs) - v ideal(@fs) v lsb where: fse is expressed in lsb v out(@fs) is the v out voltage when the dac register code is at full-scale. v ideal(@fs) is the ideal output voltage when the dac register code is at full-scale. v lsb is the delta voltage of one dac register code step (such as code 000h to code 001h). zse = v out(@zs) v lsb where: fse is expressed in lsb v out(@zs) is the v out voltage when the dac register code is at zero-scale. v lsb is the delta voltage of one dac register code step (such as code 000h to code 001h). analog output ideal transfer function actual transfer function dac input code 0 offset error (zse)
mcp4706/4716/4726 ds22272b-page 60 ? 2011 microchip technology inc. 7.7 integral nonlinearity (inl) the integral nonlinearity (inl) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). in the mcp47x6, inl is calculated using two end points (zero and full scale). inl can be expressed as a per- centage of full scale range (fsr) or in a fraction of an lsb. inl is also called relative accuracy. equation 7-4 shows how to calculate the inl error in lsb and figure 7-2 shows an example of inl accuracy. equation 7-4: inl error figure 7-2: inl accuracy example. 7.8 differential nonlinearity (dnl) the differential nonlinearity (dnl) error (see figure 7-3 ) is the measure of step size between codes in actual transfer function. the ideal step size between codes is 1 lsb. a dnl error of zero would imply that every code is exactly 1 lsb wide. if the dnl error is less than 1 lsb, the dac ensures monotonic output and no missing codes. the dnl error between any two adjacent codes is calculated as follows: equation 7-5: dnl error figure 7-3: dnl accuracy example. inl v out v ideal ? ?? lsb --------------------------------------- = where: inl is expressed in lsb. v ideal = code*lsb v out = the output voltage measured with a given dac input code 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 110 ideal transfer function actual transfer function inl = < -1 lsb inl = 0.5 lsb inl = - 1 lsb dnl ? v out lsb ? lsb --------------------------------- - = where: dnl is expressed in lsb. ? v out = the measured dac output voltage difference between two adjacent input codes. 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 dnl = 2 lsb dnl = 0.5 lsb 110 ideal transfer function actual transfer function
? 2011 microchip technology inc. ds22272b-page 61 mcp4706/4716/4726 7.9 gain error the gain error (see figure 7-4 ) is the difference between the actual full-scale output voltage from the ideal output voltage of the dac transfer curve. the gain error is calculated after nullifying the offset error, or full-scale error minus the offset error. the gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the gain error is usually expressed as percent of full-scale range (% of fsr) or in lsb. in the mcp4706/4716/4726, the gain error is not calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation near the code range beyond 4000d. for the applications that need the gain error specification less than 1% maximum, the user may consider using the dac code range between 100d and 4000d instead of using full code range (code 0 to 4095d). the dac output of the code range between 100d and 4000d is much more linear than full-scale range (0 to 4095d). the gain error can be calibrated out by software in the application. figure 7-4: gain error and full-scale error example. 7.10 gain error drift the gain error drift is the variation in gain error due to a change in ambient temperature. the gain error drift is typically expressed in ppm/ o c. 7.11 offset error drift the offset error drift is the variation in offset error due to a change in ambient temperature. the offset error drift is typically expressed in ppm/ o c. 7.12 settling time the settling time is the time delay required for the v out voltage to settle into its new output value. this time is measured from the start of code transition, to when the v out voltage is within the specified accuracy. in the mcp47x6, the settling time is a measure of the time delay until the v out voltage reaches within 0.5 lsb of its final value, when the volatile dac register changes from 400h to c00h. 7.13 major-code transition glitch major-code transition glitch is the impulse energy injected into the dac analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital code is changed by 1 lsb at the major carry transition (example: 011...111 to 100... 000 , or 100... 000 to 011 ... 111 ). 7.14 digital feedthrough the digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. the area of the glitch is expressed in nv-sec, and is measured with a full scale change (example: all 0 s to all 1 s and vice versa) on the digital input pins. the digital feedthrough is measured when the dac is not being written to the output register. 7.15 power-supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. the v out is measured while the v dd is varied +/- 10%, and expressed in db or v/v. analog output actual transfer function actual transfer function dac input code 0 gain error ideal transfer function after offset error is removed full-scale error zero-scale error
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? 2011 microchip technology inc. ds22272b-page 63 mcp4706/4716/4726 8.0 typical applications the mcp47x6 family of devices are general purpose, single channel voltage output dacs for various applications where a precision operation with low-power and nonvolatile eeprom memory is needed. since the devices include a nonvolatile eeprom memory, the user can utilize these devices for applications that require the output to return to the previous set-up value on subsequent power-ups. applications generally suited for the devices are: ? set point or offset trimming ? sensor calibration ? portable instrumentation (battery powered) ? motor control 8.1 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp47x6 devices are open-drain configurations. these pins require a pull-up resistor as shown in figure 8-2 . the pull-up resistor values (r1 and r2) for scl and sda pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the i 2 c bus line. a higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus line. therefore, it can limit the bus operating speed. the lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 1 k ?? and 10 k ?? ranges for standard and fast modes, and less than 1 k ?? for high-speed mode. 8.1.1 device connection test the user can test the presence of the device on the i 2 c bus line using a simple i 2 c command. this test can be achieved by checking an acknowledge response from the device after sending a read or write command. figure 8-1 shows an example with a read command. the steps are: a) set the r/w bit ?high? in the device?s address byte. b) check the ack bit of the address byte. if the device acknowledges (ack = 0 ) the command, then the device is connected, otherwise it is not connected. c) send stop bit. figure 8-1: i 2 c bus connection test. 12345678 9 scl sda 11 0 1 a2 a1 a0 1 start bit address byte address bits device code r/w stop bit device ack response
mcp4706/4716/4726 ds22272b-page 64 ? 2011 microchip technology inc. 8.2 power supply considerations the power source should be as clean as possible. the power supply to the device is also used for the dac voltage reference internally if the internal v dd is selected as the resistor ladders reference voltage (vref1:vref0 = 00 or 01 ). any noise induced on the v dd line can affect the dac performance. typical applications will require a bypass capacitor in order to filter out high-frequency noise on the v dd line. the noise can be induced onto the power supply?s traces or as a result of changes on the dac output. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-2 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) in parallel on the v dd line. these capacitors should be placed as close to the v dd pin as possible (within 4 mm). if the application circuit has separate digital and analog power supplies, the v dd and v ss pins of the device should reside on the analog plane. figure 8-2: example mcp47x6 circuit with sot-23 package. analog v dd 1 2 3 6 4 v dd scl sda v ss v out 5 r1 r2 to m c u r1 and r2 are i 2 c? pull-up resistors: r1 and r2: 5k ? - 10 k ? for f scl = 100 khz to 400 khz ~700 ? for f scl = 3.4 mhz c1: 0.1 f capacitor ceramic c2: 10 f capacitor tantalum c3: ~ 0.1 f optional to reduce noise in v out pin. c4: 0.1 f capacitor ceramic c5: 10 f capacitor tantalum c2 c1 mcp47x6 c3 optional (a) circuit when v dd is selected as reference ( note: v dd is connected to the reference circuit internally.) (b) circuit when external reference is used. output v ref analog v dd 1 2 3 6 4 v dd scl sda v ss v out 5 r1 r2 to m c u c2 c1 mcp47x6 c3 optional output v ref c4 optional v ref note: pin assignment is opposite in dfn-6 package. c5
? 2011 microchip technology inc. ds22272b-page 65 mcp4706/4716/4726 8.3 application examples the mcp47x6 devices are rail-to-rail output dacs designed to operate with a v dd range of 2.7v to 5.5v. the internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. the user can use gain of 1 or 2 of the output op amplifier by setting the configuration register bits. also, the user can use internal v dd as the reference or use external reference. various user options and easy-to-use features make the devices suitable for various modern dac applications. application examples include: ? decreasing output step size ? building a ?window? dac ? bipolar operation ? selectable gain and offset bipolar voltage output ? designing a double-precision dac ? building programmable current source ? serial interface communication times ? software i2c interface reset sequence ? power supply considerations ? layout considerations 8.3.1 dc set point or calibration a common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. for example, the mcp4726 provides 4096 output steps. if voltage reference is 4.096v, the lsb size is 1 mv. if a smaller output step size is desired, a lower external voltage reference is needed. 8.3.1.1 decreasing output step size if the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8v may be desired with about 200 v resolution per step. two common methods to achieve small step size are using lower v ref pin voltage or using a voltage divider on the dac?s output. using an external voltage reference (v ref ) is an option, if the external reference is available with the desired output voltage range. however, occasionally, when using a low-voltage reference voltage, the noise floor causes a snr error that is intolerable. using a voltage divider method is another option, and provides some advantages when external voltage reference needs to be very low, or when the desired output voltage is not available. in this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. figure 8-3 illustrates this concept. a bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. figure 8-3: example circuit of set point or threshold calibration. equation 8-1: v out and v trip calculations r 1 v cc + v cc ? v out i 2 c? 2-wire v ref optional mcp47x6 v dd v o r 2 c 1 r sense comp. v dd v trip v trip v out r 2 r 1 r 2 + -------------------- ?? ?? ?? = v out = v ref ? g ? dac register value 2 n
mcp4706/4716/4726 ds22272b-page 66 ? 2011 microchip technology inc. 8.3.1.2 building a ?window? dac when calibrating a set point or threshold of a sensor, typically only a small portion of the dac output range is utilized. if the lsb size is adequate enough to meet the application?s accuracy needs, the unused range is sacrificed without consequences. if greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. if the threshold is not near v ref , 2 ? v ref , or v ss then creating a ?window? around the threshold has several advantages. one simple method to create this ?window? is to use a voltage divider network with a pull-up and pull-down resistor. figure 8-4 and figure 8-6 illustrate this concept. figure 8-4: single-supply ?window? dac. equation 8-2: v out and v trip calculations 8.4 bipolar operation bipolar operation is achievable by utilizing an external operational amplifier. this configuration is desirable due to the wide variety and availability of op amps. this allows a general purpose dac, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. figure 8-5 illustrates a simple bipolar voltage source configuration. r 1 and r 2 allow the gain to be selected, while r 3 and r 4 shift the dac's output to a selected offset. note that r4 can be tied to v dd , instead of v ss , if a higher offset is desired. figure 8-5: digitally-controlled bipolar voltage source example circuit. equation 8-3: v out , v oa+ , and v o calculations r 1 v cc + v cc ? v o i 2 c? 2-wire v ref optional mcp47x6 v dd v out r 2 c 1 r 3 v cc + v cc ? r sense comp. v trip r 23 r 2 r 3 r 2 r 3 + ------------------- = v 23 v cc+ r 2 ?? v cc- r 3 ?? + r 2 r 3 + ------------------------------------------------------ = v trip v out r 23 v 23 r 1 + r 1 r 23 + -------------------------------------------- - = thevenin equivalent r 1 r 23 v 23 v out v trip v out = v ref ? g ? dac register value 2 n r 3 v cc + v cc ? v o i 2 c? 2-wire v ref optional mcp47x6 v dd r 2 v out v in r 1 r 4 c 1 v oa+ v oa+ = v out ? r 4 r 3 + r 4 v out = v ref ? g ? dac register value 2 n v o = v oa+ ? ( 1 + ) - v dd ? ( ) r 2 r 1 r 2 r 1
? 2011 microchip technology inc. ds22272b-page 67 mcp4706/4716/4726 8.5 selectable gain and offset bipolar voltage output in some applications, precision digital control of the output range is desirable. figure 8-6 illustrates how to use the dac devices to achieve this in a bipolar or single-supply application. this circuit is typically used for linearizing a sensor whose slope and offset varies. the equation to design a bipolar ?window? dac would be utilized if r 3 , r 4 and r 5 are populated. 8.5.1 bipolar dac example using mcp4726 an output step size of 1 mv, with an output range of 2.05v, is desired for a particular application. step 1: calculate the range: +2.05v ? (-2.05v) = 4.1v. step 2: calculate the resolution needed: 4.1v/1 mv = 4100 since 2 12 = 4096, 12-bit resolution is desired. step 3: the amplifier gain (r 2 /r 1 ), multiplied by full-scale v out (4.096v), must be equal to the desired minimum output to achieve bipolar operation. since any gain can be realized by choosing resistor values (r 1 +r 2 ), the v ref value must be selected first. if a v ref of 4.096v is used, solve for the amplifier?s gain by setting the dac to 0, knowing that the output needs to be -2.05v. the equation can be simplified to: step 4: next, solve for r 3 and r 4 by setting the dac to 4096, knowing that the output needs to be +2.05v. figure 8-6 (c1 = 0.1uf) figure 8-6: bipolar voltage source with selectable gain and offset. equation 8-4: v out , v oa+ , and v o calculations equation 8-5: bipolar ?window? dac using r 4 and r 5 r 2 ? r 1 -------- - 2.05 ? 4.096v ---------------- - = if r 1 = 20 k ? and r 2 = 10 k ? , the gain will be 0.5. r 2 r 1 ----- - 1 2 -- - = r 4 r 3 r 4 + ?? ----------------------- - 2.05v 0.5 4.096v ? ?? + 1.5 4.096v ? ------------------------------------------------------- 2 3 -- - == if r 4 = 20 k ? , then r 3 = 10 k ? r 3 v cc + v cc ? v out i 2 c? 2-wire v ref optional mcp4726 v dd r 2 v o v in r 1 r 4 c 1 r 5 optional v oa+ v cc + v cc ? offset adjust gain adjust v out = v ref ? g ? dac register value 2 n v oa+ = v out ? r 4 + v cc- ? r 5 r 3 + r 4 v o = v oa+ ? ( 1 + ) - v in ? ( ) r 2 r 1 r 2 r 1 thevenin equivalent v 45 v cc+ r 4 v cc- r 5 + r 4 r 5 + -------------------------------------------- - = v in+ v out r 45 v 45 r 3 + r 3 r 45 + -------------------------------------------- - = r 45 r 4 r 5 r 4 r 5 + ------------------ - = v o v in+ 1 r 2 r 1 ----- - + ?? ?? v a r 2 r 1 ----- - ?? ?? ? = offset adjust gain adjust
mcp4706/4716/4726 ds22272b-page 68 ? 2011 microchip technology inc. 8.6 designing a double-precision dac figure 8-7 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. this requires two 12-bit dacs. this design is simply a voltage divider with a buffered output. as an example, if a similar application to the one developed in section 8.5.1 ?bipolar dac example using mcp4726? required a resolution of 1 v instead of 1 mv, and a range of 0v to 4.1v, then 12-bit resolution would not be adequate. step 1: calculate the resolution needed: 4.1v/1 v = 4.1 x 10 6 . since 2 22 =4.2x10 6 , 22-bit resolution is desired. since dnl = 0.75 lsb, this design can be attempted with the 12-bit dac. step 2: since dac b ?s v outb has a resolution of 1 mv, its output only needs to be ?pulled? 1/1000 to meet the 1 v target. dividing v outa by 1000 would allow the application to compensate for dac b ?s dnl error. step 3: if r 2 is 100 ? , then r 1 needs to be 100 k ? . step 4: the resulting transfer function is shown in the equation of example 8-6 . figure 8-7: simple double precision dac using mcp4726. equation 8-6: v out calculation 8.7 building programmable current source figure 8-8 shows an example of building programmable current source using a voltage follower. the current sensor resistor is used to convert the dac voltage output into a digitally-selectable current source. the smaller r sense is, the less power dissipated across it. however, this also reduces the resolution that the current can be controlled. figure 8-8: digitally-controlled current source. r 1 v cc + v cc ? v out i 2 c? 2-wire v ref optional mcp4726 (a) v dd i 2 c? 2-wire v ref optional mcp4726 (b) v dd r 2 0.1 f v oa v ob v out = g = selected op amp gain v oa * r 2 + v ob * r 1 r 1 + r 2 v oa = (v ref * g * dac a register value)/4096 v ob = (v ref * g * dac b register value)/4096 where: r sense i b load i l v cc + v cc ? v out i l v out r sense -------------- - ? ? 1 + ------------ - ? = i b i l ? ---- = ??? ? common-emitter current gain ?? where v dd i 2 c? 2-wire v ref optional mcp47x6 v dd (or v ref )
? 2011 microchip technology inc. ds22272b-page 69 mcp4706/4716/4726 8.8 serial interface communication times table 8-1 shows time/frequency of the supported operations of the i 2 c serial interface for the different serial interface operational frequencies. this, along with the v out output performance (such as slew rate), would be used to determine your applications volatile dac register update rate. table 8-1: serial interface times / frequencies command writes volatile memory? writes eeprom memory? # of serial interface bits (2) command time (us) command frequency (khz) code function c2 c1 c0 config. dac config. dac 100khz400khz3.4mhz100khz400khz3.4mhz 00x write volatile dac yes (1) yes no no 29 290 72.5 8.5 3.4 13.8 117.2 010 write volatile memory yes yes no no 38 380 95 11.2 2.6 10.5 89.5 011 write all memory yes yes yes yes 38 380 95 11.2 2.6 10.5 89.5 100 write nv configuration bits yes no no no 20 200 50 5.9 5.0 20.0 170.0 n/a read n/a n/a n/a n/a 77 750 187.5 22.1 1.3 5.3 45.3 note 1: only the volatile pd1:pd0 bits of the configuration bits are written. 2: includes the start or stop bits.
mcp4706/4716/4726 ds22272b-page 70 ? 2011 microchip technology inc. 8.9 software i 2 c interface reset sequence at times, it may become necessary to perform a software reset sequence to ensure the mcp47x6 device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp47x6 device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. figure 8-9 shows the communication sequence to software reset the device. figure 8-9: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. in this mode, the device is monitoring the data bus in receive mode and can detect if the start bit forces an internal reset. the nine bits of ? 1 ? are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp47x6 is driving an a bit on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of ? 0 ? onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp47x6 holding the bus low. by sending out nine ? 1 ? bits, it is ensured that the device will see an a bit (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp47x6), which also forces the mcp47x6 to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp47x6, and then as the master device returns to normal operation and issues a start condition, while the mcp47x6 is issuing an acknowledge. in this case, if the 2nd start bit is not sent (and the stop bit was sent) the mcp47x6 could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp47x6 waits to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. note: this technique is documented in an1028. s? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ? s p start bit nine bits of ? 1 ? start bit stop bit note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp47x6.
? 2011 microchip technology inc. ds22272b-page 71 mcp4706/4716/4726 8.10 design considerations in the design of a system with the mcp4706/4716/4726 devices, the following considerations should be taken into account: ? power supply considerations ? layout considerations 8.10.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-10 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-10: typical microcontroller connections. 8.10.2 layout considerations several layout considerations may be applicable to your application. these may include: ? noise ? pcb area requirements 8.10.2.1 noise inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp47x6?s performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. separate digital and analog ground planes are recommended. in this case, the v ss pin and the ground pins of the v dd capacitors should be terminated to the analog ground plane. 8.10.2.2 pcb area requirements in some applications, pcb area is a criteria for device selection. tab l e 8 - 2 shows the typical package dimensions and area for the different package options. the table also shows the relative area factor compared to the smallest area. for space critical applications, the dfn package would be the suggested package. table 8-2: package footprint ( 1 ) v dd v dd v ss v ss mcp47x6 0.1 f pic ? microcontroller 0.1 f scl v out v ref sda note: breadboards and wire-wrapped boards are not recommended. package package footprint pins type code dimensions (mm) area (mm 2 ) relative area length width 6 sot-23 ch 2.90 2.70 7.83 1.96 6 dfn ma 2.00 2.00 4.00 1 note 1: does not include recommended land pattern dimensions. dimensions are typical values.
mcp4706/4716/4726 ds22272b-page 72 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22272b-page 73 mcp4706/4716/4726 9.0 development support development support can be classified into two groups. these are: ? development tools ? technical documentation 9.1 development tools several development tools are available to assist in your design and evaluation of the mcp47x6 devices. the currently available tools are shown in ta bl e 9 - 1 . these boards may be purchased directly from the microchip web site at www.microchip.com. 9.1.1 mcp47x6 pictail? plus daughter board the mcp47x6 pictail plus daughter board (order number: adm00317) is available from microchip technology inc. this board works with microchip?s pickit? serial analyzer and pic ? explorer 16 development board. the firmware example is also available for the explore 16 development board with pic24fj128. figure 9-1 shows the mcp47x6 pictail plus daughter board being used with a pic explorer 16 development board (order #: adm00317), while figure 9-2 shows the mcp47x6 pictail plus daughter board being used with a pickit? serial analyzer. the pickit? serial analyzer allows the user to quickly evaluate the dac operation. refer to the ? mcp47x6 pictail? plus daughter board user?s guide ? (ds51932) for detailed descriptions on operating the daughter board. refer to www.microchip.com for further information on this product and related material for the users. figure 9-1: mcp47x6 pictail plus daughter board with pic explorer 16 development board. figure 9-2: mcp47x6 pictail plus daughter board with pickit? serial analyzer. table 9-1: development tools mcp47x6 pictail? plus explore 16 daughter board inserted into pictail connector development board mcp47x6 pictail? plus daughter board board name part # supported devices 6-pin sc70 evaluation board sc70ev mcp4706, mcp4716, mcp4726 mcp4706/4716/4726 evaluation board (1, 2) adm00317 mcp4726 note 1: requires a picdem? demo board. see the user?s guide for additional information and requirements. 2: requires a pickit serial analyzer. see the user?s guide for additional information and requirements.
mcp4706/4716/4726 ds22272b-page 74 ? 2011 microchip technology inc. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. tab l e 9 - 2 shows some of these documents. table 9-2: technical documentation application note number title literature # an1326 using dac for ldmos amplifier bias control applications ds01326 ? signal chain design guide ds21825 ? analog solutions for automotive applications design guide ds01005
? 2011 microchip technology inc. ds22272b-page 75 mcp4706/4716/4726 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 6-lead sot-23 xxnn xxx 6-lead dfn (2x2) nnn aab example 425 example dc25 address option code mcp4706a0t-e/ch mcp4716a0t-e/ch mcp4726a0t-e/ch a0 (00) dbnn dfnn dknn a1 (01) dcnn dgnn dlnn a2 (10) ddnn dhnn dmnn a3 (11) denn djnn dpnn address option code mcp4706a0t-e/ma mcp4716a0t-e/ma mcp4726a0t-e/ma a0 (00) aaa aae aap a1 (01) aab aaf aaq a2 (10) aac aag aar a3 (11) aad aah aas
mcp4706/4716/4726 ds22272b-page 76 ? 2011 microchip technology inc. b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1
? 2011 microchip technology inc. ds22272b-page 77 mcp4706/4716/4726 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp4706/4716/4726 ds22272b-page 78 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22272b-page 79 mcp4706/4716/4726 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp4706/4716/4726 ds22272b-page 80 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22272b-page 81 mcp4706/4716/4726 appendix a: revision history revision b (september 2011) ? updated references to graphics and equations in the text. ? updated notes in figure 6-6: ?read command format for 8-bit dac (mcp4706).? revision a (february 2011) ? original release of this document.
mcp4706/4716/4726 ds22272b-page 82 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22272b-page 83 mcp4706/4716/4726 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp4706: single channel 8-bit dac with eeprom memory mcp4716: single channel 10-bit dac with eeprom memory mcp4726: single channel 12-bit dac with eeprom memory address options: a0 = ? 1100000 ? i 2 c address. devices ordered from the microchip sample center will have this address. a1 = ? 1100001 ? i 2 c address. a2 = ? 1100010 ? i 2 c address. a3 = ? 1100011 ? i 2 c address. a4 = ? 1100100 ? i 2 c address. a5 = ? 1100101 ? i 2 c address. a6 = ? 1100110 ? i 2 c address. a7 = ? 1100111 ? i 2 c address. tape and reel: t = tape and reel temperature range: e = -40c to +125c package: ch = plastic small outline transistor (sot-23-6), 6-lead ma = plastic dual flat, no lead package (2x2 dfn), 6-lead examples: a) mcp4706a0t-e/ch: 8-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld sot-23 pkg. b) mcp4706a6t-e/ch: 8-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld sot-23 pkg. c) mcp4706a0t-e/ma: 8-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld dfn pkg. d) mcp4706a6t-e/ma: 8-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld dfn pkg. a) mcp4716a0t-e/ch: 10-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld sot-23 pkg. b) mcp4716a6t-e/ch: 10-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld sot-23 pkg. c) mcp4716a0t-e/ma: 10-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld dfn pkg. d) mcp4716a6t-e/ma: 10-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld dfn pkg. a) mcp4726a0t-e/ch: 12-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld sot-23 pkg. b) mcp4726a6t-e/ch: 12-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld sot-23 pkg. c) mcp4726a0t-e/ma: 12-bit v out resolution, i 2 c address ? 1100000 ?, tape and reel, extended temp., 6ld dfn pkg. d) mcp4726a6t-e/ma: 12-bit v out resolution, i 2 c address ? 1100110 ?, tape and reel, extended temp., 6ld dfn pkg. part no. x xx address temperature range device /xx package options x tape and reel
mcp4706/4716/4726 ds22272b-page 84 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22272b-page 85 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-669-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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